Documentation/devicetree/bindings/ipmi/aspeed,ast2400-kcs-bmc.yaml

   1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
   2 %YAML 1.2
   3 ---
   4 $id: http://devicetree.org/schemas/ipmi/aspeed,ast2400-kcs-bmc.yaml#
   5 $schema: http://devicetree.org/meta-schemas/core.yaml#
   6
   7 title: ASPEED BMC KCS Devices
   8
   9 maintainers:
  10   - Andrew Jeffery <andrew@aj.id.au>
  11
  12 description: |
  13   The Aspeed BMC SoCs typically use the Keyboard-Controller-Style (KCS)
  14   interfaces on the LPC bus for in-band IPMI communication with their host.
  15
  16 properties:
  17   compatible:
  18     oneOf:
  19       - description: Channel ID derived from reg
  20         items:
  21           enum:
  22             - aspeed,ast2400-kcs-bmc-v2
  23             - aspeed,ast2500-kcs-bmc-v2
  24             - aspeed,ast2600-kcs-bmc
  25
  26       - description: Old-style with explicit channel ID, no reg
  27         deprecated: true
  28         items:
  29           enum:
  30             - aspeed,ast2400-kcs-bmc
  31             - aspeed,ast2500-kcs-bmc
  32
  33   interrupts:
  34     maxItems: 1
  35
  36   reg:
  37     # maxItems: 3
  38     items:
  39       - description: IDR register
  40       - description: ODR register
  41       - description: STR register
  42
  43   aspeed,lpc-io-reg:
  44     $ref: '/schemas/types.yaml#/definitions/uint32-array'
  45     minItems: 1
  46     maxItems: 2
  47     description: |
  48       The host CPU LPC IO data and status addresses for the device. For most
  49       channels the status address is derived from the data address, but the
  50       status address may be optionally provided.
  51
  52   aspeed,lpc-interrupts:
  53     $ref: "/schemas/types.yaml#/definitions/uint32-array"
  54     minItems: 2
  55     maxItems: 2
  56     description: |
  57       A 2-cell property expressing the LPC SerIRQ number and the interrupt
  58       level/sense encoding (specified in the standard fashion).
  59
  60       Note that the generated interrupt is issued from the BMC to the host, and
  61       thus the target interrupt controller is not captured by the BMC's
  62       devicetree.
  63
  64   kcs_chan:
  65     deprecated: true
  66     $ref: '/schemas/types.yaml#/definitions/uint32'
  67     description: The LPC channel number in the controller
  68
  69   kcs_addr:
  70     deprecated: true
  71     $ref: '/schemas/types.yaml#/definitions/uint32'
  72     description: The host CPU IO map address
  73
  74 required:
  75   - compatible
  76   - interrupts
  77
  78 additionalProperties: false
  79
  80 allOf:
  81   - if:
  82       properties:
  83         compatible:
  84           contains:
  85             enum:
  86               - aspeed,ast2400-kcs-bmc
  87               - aspeed,ast2500-kcs-bmc
  88     then:
  89       required:
  90         - kcs_chan
  91         - kcs_addr
  92     else:
  93       required:
  94         - reg
  95         - aspeed,lpc-io-reg
  96
  97 examples:
  98   - |
  99     #include <dt-bindings/interrupt-controller/irq.h>
 100     kcs3: kcs@24 {
 101         compatible = "aspeed,ast2600-kcs-bmc";
 102         reg = <0x24 0x1>, <0x30 0x1>, <0x3c 0x1>;
 103         aspeed,lpc-io-reg = <0xca2>;
 104         aspeed,lpc-interrupts = <11 IRQ_TYPE_LEVEL_LOW>;
 105         interrupts = <8>;
 106     };