Documentation/devicetree/bindings/interconnect/qcom,osm-l3.yaml

   1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
   2 %YAML 1.2
   3 ---
   4 $id: http://devicetree.org/schemas/interconnect/qcom,osm-l3.yaml#
   5 $schema: http://devicetree.org/meta-schemas/core.yaml#
   6
   7 title: Qualcomm Operating State Manager (OSM) L3 Interconnect Provider
   8
   9 maintainers:
  10   - Sibi Sankar <sibis@codeaurora.org>
  11
  12 description:
  13   L3 cache bandwidth requirements on Qualcomm SoCs is serviced by the OSM.
  14   The OSM L3 interconnect provider aggregates the L3 bandwidth requests
  15   from CPU/GPU and relays it to the OSM.
  16
  17 properties:
  18   compatible:
  19     enum:
  20       - qcom,sc7180-osm-l3
  21       - qcom,sc8180x-osm-l3
  22       - qcom,sdm845-osm-l3
  23       - qcom,sm8150-osm-l3
  24       - qcom,sm8250-epss-l3
  25
  26   reg:
  27     maxItems: 1
  28
  29   clocks:
  30     items:
  31       - description: xo clock
  32       - description: alternate clock
  33
  34   clock-names:
  35     items:
  36       - const: xo
  37       - const: alternate
  38
  39   '#interconnect-cells':
  40     const: 1
  41
  42 required:
  43   - compatible
  44   - reg
  45   - clocks
  46   - clock-names
  47   - '#interconnect-cells'
  48
  49 additionalProperties: false
  50
  51 examples:
  52   - |
  53
  54     #define GPLL0               165
  55     #define RPMH_CXO_CLK        0
  56
  57     osm_l3: interconnect@17d41000 {
  58       compatible = "qcom,sdm845-osm-l3";
  59       reg = <0x17d41000 0x1400>;
  60
  61       clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>;
  62       clock-names = "xo", "alternate";
  63
  64       #interconnect-cells = <1>;
  65     };