1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 $id: http://devicetree.org/schemas/iio/adc/renesas,rzg2l-adc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Renesas RZ/G2L ADC
10 - Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
13 A/D Converter block is a successive approximation analog-to-digital converter
14 with a 12-bit accuracy. Up to eight analog input channels can be selected.
15 Conversions can be performed in single or repeat mode. Result of the ADC is
16 stored in a 32-bit data register corresponding to each channel.
22 - renesas,r9a07g044-adc # RZ/G2{L,LC}
23 - const: renesas,rzg2l-adc
33 - description: converter clock
34 - description: peripheral clock
73 Represents the external channels which are connected to the ADC.
78 The channel number. It can have up to 8 channels numbered from 0 to 7.
86 additionalProperties: false
88 additionalProperties: false
92 #include <dt-bindings/clock/r9a07g044-cpg.h>
93 #include <dt-bindings/interrupt-controller/arm-gic.h>
96 compatible = "renesas,r9a07g044-adc", "renesas,rzg2l-adc";
97 reg = <0x10059000 0x400>;
98 interrupts = <GIC_SPI 347 IRQ_TYPE_EDGE_RISING>;
99 clocks = <&cpg CPG_MOD R9A07G044_ADC_ADCLK>,
100 <&cpg CPG_MOD R9A07G044_ADC_PCLK>;
101 clock-names = "adclk", "pclk";
102 power-domains = <&cpg>;
103 resets = <&cpg R9A07G044_ADC_PRESETN>,
104 <&cpg R9A07G044_ADC_ADRST_N>;
105 reset-names = "presetn", "adrst-n";
107 #address-cells = <1>;