Documentation/devicetree/bindings/iio/adc/renesas,rzg2l-adc.yaml

   1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
   2 %YAML 1.2
   3 ---
   4 $id: http://devicetree.org/schemas/iio/adc/renesas,rzg2l-adc.yaml#
   5 $schema: http://devicetree.org/meta-schemas/core.yaml#
   6
   7 title: Renesas RZ/G2L ADC
   8
   9 maintainers:
  10   - Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
  11
  12 description: |
  13   A/D Converter block is a successive approximation analog-to-digital converter
  14   with a 12-bit accuracy. Up to eight analog input channels can be selected.
  15   Conversions can be performed in single or repeat mode. Result of the ADC is
  16   stored in a 32-bit data register corresponding to each channel.
  17
  18 properties:
  19   compatible:
  20     items:
  21       - enum:
  22           - renesas,r9a07g044-adc   # RZ/G2{L,LC}
  23       - const: renesas,rzg2l-adc
  24
  25   reg:
  26     maxItems: 1
  27
  28   interrupts:
  29     maxItems: 1
  30
  31   clocks:
  32     items:
  33       - description: converter clock
  34       - description: peripheral clock
  35
  36   clock-names:
  37     items:
  38       - const: adclk
  39       - const: pclk
  40
  41   power-domains:
  42     maxItems: 1
  43
  44   resets:
  45     maxItems: 2
  46
  47   reset-names:
  48     items:
  49       - const: presetn
  50       - const: adrst-n
  51
  52   '#address-cells':
  53     const: 1
  54
  55   '#size-cells':
  56     const: 0
  57
  58 required:
  59   - compatible
  60   - reg
  61   - interrupts
  62   - clocks
  63   - clock-names
  64   - power-domains
  65   - resets
  66   - reset-names
  67
  68 patternProperties:
  69   "^channel@[0-7]$":
  70     $ref: "adc.yaml"
  71     type: object
  72     description: |
  73       Represents the external channels which are connected to the ADC.
  74
  75     properties:
  76       reg:
  77         description: |
  78           The channel number. It can have up to 8 channels numbered from 0 to 7.
  79         items:
  80           - minimum: 0
  81             maximum: 7
  82
  83     required:
  84       - reg
  85
  86     additionalProperties: false
  87
  88 additionalProperties: false
  89
  90 examples:
  91   - |
  92     #include <dt-bindings/clock/r9a07g044-cpg.h>
  93     #include <dt-bindings/interrupt-controller/arm-gic.h>
  94
  95     adc: adc@10059000 {
  96       compatible = "renesas,r9a07g044-adc", "renesas,rzg2l-adc";
  97       reg = <0x10059000 0x400>;
  98       interrupts = <GIC_SPI 347 IRQ_TYPE_EDGE_RISING>;
  99       clocks = <&cpg CPG_MOD R9A07G044_ADC_ADCLK>,
 100                <&cpg CPG_MOD R9A07G044_ADC_PCLK>;
 101       clock-names = "adclk", "pclk";
 102       power-domains = <&cpg>;
 103       resets = <&cpg R9A07G044_ADC_PRESETN>,
 104                <&cpg R9A07G044_ADC_ADRST_N>;
 105       reset-names = "presetn", "adrst-n";
 106
 107       #address-cells = <1>;
 108       #size-cells = <0>;
 109
 110       channel@0 {
 111         reg = <0>;
 112       };
 113       channel@1 {
 114         reg = <1>;
 115       };
 116       channel@2 {
 117         reg = <2>;
 118       };
 119       channel@3 {
 120         reg = <3>;
 121       };
 122       channel@4 {
 123         reg = <4>;
 124       };
 125       channel@5 {
 126         reg = <5>;
 127       };
 128       channel@6 {
 129         reg = <6>;
 130       };
 131       channel@7 {
 132         reg = <7>;
 133       };
 134     };