1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 $id: http://devicetree.org/schemas/fpga/xilinx-zynq-fpga-mgr.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Xilinx Zynq FPGA Manager Device Tree Bindings
10 - Michal Simek <michal.simek@xilinx.com>
14 const: xlnx,zynq-devcfg-1.0
30 $ref: /schemas/types.yaml#/definitions/phandle
32 Phandle to syscon block which provide access to SLCR registers
41 additionalProperties: false
45 devcfg: devcfg@f8007000 {
46 compatible = "xlnx,zynq-devcfg-1.0";
47 reg = <0xf8007000 0x100>;
50 clock-names = "ref_clk";