Documentation/devicetree/bindings/dma/ti/k3-pktdma.yaml

   1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
   2 %YAML 1.2
   3 ---
   4 $id: http://devicetree.org/schemas/dma/ti/k3-pktdma.yaml#
   5 $schema: http://devicetree.org/meta-schemas/core.yaml#
   6
   7 title: Texas Instruments K3 DMSS PKTDMA Device Tree Bindings
   8
   9 maintainers:
  10   - Peter Ujfalusi <peter.ujfalusi@ti.com>
  11
  12 description: |
  13   The Packet DMA (PKTDMA) is intended to perform similar functions as the packet
  14   mode channels of K3 UDMA-P.
  15   PKTDMA only includes Split channels to service PSI-L based peripherals.
  16
  17   The peripherals can be PSI-L native or legacy, non PSI-L native peripherals
  18   with PDMAs. PDMA is tasked to act as a bridge between the PSI-L fabric and the
  19   legacy peripheral.
  20
  21   PDMAs can be configured via PKTDMA split channel's peer registers to match
  22   with the configuration of the legacy peripheral.
  23
  24 allOf:
  25   - $ref: /schemas/dma/dma-controller.yaml#
  26
  27 properties:
  28   compatible:
  29     const: ti,am64-dmss-pktdma
  30
  31   "#dma-cells":
  32     const: 2
  33     description: |
  34       The first cell is the PSI-L  thread ID of the remote (to PKTDMA) end.
  35       Valid ranges for thread ID depends on the data movement direction:
  36       for source thread IDs (rx): 0 - 0x7fff
  37       for destination thread IDs (tx): 0x8000 - 0xffff
  38
  39       Please refer to the device documentation for the PSI-L thread map and also
  40       the PSI-L peripheral chapter for the correct thread ID.
  41
  42       The second cell is the ASEL value for the channel
  43
  44   reg:
  45     maxItems: 4
  46
  47   reg-names:
  48     items:
  49       - const: gcfg
  50       - const: rchanrt
  51       - const: tchanrt
  52       - const: ringrt
  53
  54   msi-parent: true
  55
  56   ti,sci-rm-range-tchan:
  57     $ref: /schemas/types.yaml#/definitions/uint32-array
  58     description: |
  59       Array of PKTDMA split tx channel resource subtypes for resource allocation
  60       for this host
  61     minItems: 1
  62     # Should be enough
  63     maxItems: 255
  64     items:
  65       maximum: 0x3f
  66
  67   ti,sci-rm-range-tflow:
  68     $ref: /schemas/types.yaml#/definitions/uint32-array
  69     description: |
  70       Array of PKTDMA split tx flow resource subtypes for resource allocation
  71       for this host
  72     minItems: 1
  73     # Should be enough
  74     maxItems: 255
  75     items:
  76       maximum: 0x3f
  77
  78   ti,sci-rm-range-rchan:
  79     $ref: /schemas/types.yaml#/definitions/uint32-array
  80     description: |
  81       Array of PKTDMA split rx channel resource subtypes for resource allocation
  82       for this host
  83     minItems: 1
  84     # Should be enough
  85     maxItems: 255
  86     items:
  87       maximum: 0x3f
  88
  89   ti,sci-rm-range-rflow:
  90     $ref: /schemas/types.yaml#/definitions/uint32-array
  91     description: |
  92       Array of PKTDMA split rx flow resource subtypes for resource allocation
  93       for this host
  94     minItems: 1
  95     # Should be enough
  96     maxItems: 255
  97     items:
  98       maximum: 0x3f
  99
 100 required:
 101   - compatible
 102   - "#dma-cells"
 103   - reg
 104   - reg-names
 105   - msi-parent
 106   - ti,sci
 107   - ti,sci-dev-id
 108   - ti,sci-rm-range-tchan
 109   - ti,sci-rm-range-tflow
 110   - ti,sci-rm-range-rchan
 111   - ti,sci-rm-range-rflow
 112
 113 unevaluatedProperties: false
 114
 115 examples:
 116   - |+
 117     cbass_main {
 118         #address-cells = <2>;
 119         #size-cells = <2>;
 120
 121         main_dmss {
 122             compatible = "simple-mfd";
 123             #address-cells = <2>;
 124             #size-cells = <2>;
 125             dma-ranges;
 126             ranges;
 127
 128             ti,sci-dev-id = <25>;
 129
 130             main_pktdma: dma-controller@485c0000 {
 131                 compatible = "ti,am64-dmss-pktdma";
 132
 133                 reg = <0x0 0x485c0000 0x0 0x100>,
 134                       <0x0 0x4a800000 0x0 0x20000>,
 135                       <0x0 0x4aa00000 0x0 0x40000>,
 136                       <0x0 0x4b800000 0x0 0x400000>;
 137                 reg-names = "gcfg", "rchanrt", "tchanrt", "ringrt";
 138                 msi-parent = <&inta_main_dmss>;
 139                 #dma-cells = <2>;
 140
 141                 ti,sci = <&dmsc>;
 142                 ti,sci-dev-id = <30>;
 143
 144                 ti,sci-rm-range-tchan = <0x23>, /* UNMAPPED_TX_CHAN */
 145                                         <0x24>, /* CPSW_TX_CHAN */
 146                                         <0x25>, /* SAUL_TX_0_CHAN */
 147                                         <0x26>, /* SAUL_TX_1_CHAN */
 148                                         <0x27>, /* ICSSG_0_TX_CHAN */
 149                                         <0x28>; /* ICSSG_1_TX_CHAN */
 150                 ti,sci-rm-range-tflow = <0x10>, /* RING_UNMAPPED_TX_CHAN */
 151                                         <0x11>, /* RING_CPSW_TX_CHAN */
 152                                         <0x12>, /* RING_SAUL_TX_0_CHAN */
 153                                         <0x13>, /* RING_SAUL_TX_1_CHAN */
 154                                         <0x14>, /* RING_ICSSG_0_TX_CHAN */
 155                                         <0x15>; /* RING_ICSSG_1_TX_CHAN */
 156                 ti,sci-rm-range-rchan = <0x29>, /* UNMAPPED_RX_CHAN */
 157                                         <0x2b>, /* CPSW_RX_CHAN */
 158                                         <0x2d>, /* SAUL_RX_0_CHAN */
 159                                         <0x2f>, /* SAUL_RX_1_CHAN */
 160                                         <0x31>, /* SAUL_RX_2_CHAN */
 161                                         <0x33>, /* SAUL_RX_3_CHAN */
 162                                         <0x35>, /* ICSSG_0_RX_CHAN */
 163                                         <0x37>; /* ICSSG_1_RX_CHAN */
 164                 ti,sci-rm-range-rflow = <0x2a>, /* FLOW_UNMAPPED_RX_CHAN */
 165                                         <0x2c>, /* FLOW_CPSW_RX_CHAN */
 166                                         <0x2e>, /* FLOW_SAUL_RX_0/1_CHAN */
 167                                         <0x32>, /* FLOW_SAUL_RX_2/3_CHAN */
 168                                         <0x36>, /* FLOW_ICSSG_0_RX_CHAN */
 169                                         <0x38>; /* FLOW_ICSSG_1_RX_CHAN */
 170             };
 171         };
 172     };