1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 $id: http://devicetree.org/schemas/dma/ti/k3-pktdma.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Texas Instruments K3 DMSS PKTDMA Device Tree Bindings
10 - Peter Ujfalusi <peter.ujfalusi@ti.com>
13 The Packet DMA (PKTDMA) is intended to perform similar functions as the packet
14 mode channels of K3 UDMA-P.
15 PKTDMA only includes Split channels to service PSI-L based peripherals.
17 The peripherals can be PSI-L native or legacy, non PSI-L native peripherals
18 with PDMAs. PDMA is tasked to act as a bridge between the PSI-L fabric and the
21 PDMAs can be configured via PKTDMA split channel's peer registers to match
22 with the configuration of the legacy peripheral.
25 - $ref: /schemas/dma/dma-controller.yaml#
29 const: ti,am64-dmss-pktdma
34 The first cell is the PSI-L thread ID of the remote (to PKTDMA) end.
35 Valid ranges for thread ID depends on the data movement direction:
36 for source thread IDs (rx): 0 - 0x7fff
37 for destination thread IDs (tx): 0x8000 - 0xffff
39 Please refer to the device documentation for the PSI-L thread map and also
40 the PSI-L peripheral chapter for the correct thread ID.
42 The second cell is the ASEL value for the channel
56 ti,sci-rm-range-tchan:
57 $ref: /schemas/types.yaml#/definitions/uint32-array
59 Array of PKTDMA split tx channel resource subtypes for resource allocation
67 ti,sci-rm-range-tflow:
68 $ref: /schemas/types.yaml#/definitions/uint32-array
70 Array of PKTDMA split tx flow resource subtypes for resource allocation
78 ti,sci-rm-range-rchan:
79 $ref: /schemas/types.yaml#/definitions/uint32-array
81 Array of PKTDMA split rx channel resource subtypes for resource allocation
89 ti,sci-rm-range-rflow:
90 $ref: /schemas/types.yaml#/definitions/uint32-array
92 Array of PKTDMA split rx flow resource subtypes for resource allocation
108 - ti,sci-rm-range-tchan
109 - ti,sci-rm-range-tflow
110 - ti,sci-rm-range-rchan
111 - ti,sci-rm-range-rflow
113 unevaluatedProperties: false
118 #address-cells = <2>;
122 compatible = "simple-mfd";
123 #address-cells = <2>;
128 ti,sci-dev-id = <25>;
130 main_pktdma: dma-controller@485c0000 {
131 compatible = "ti,am64-dmss-pktdma";
133 reg = <0x0 0x485c0000 0x0 0x100>,
134 <0x0 0x4a800000 0x0 0x20000>,
135 <0x0 0x4aa00000 0x0 0x40000>,
136 <0x0 0x4b800000 0x0 0x400000>;
137 reg-names = "gcfg", "rchanrt", "tchanrt", "ringrt";
138 msi-parent = <&inta_main_dmss>;
142 ti,sci-dev-id = <30>;
144 ti,sci-rm-range-tchan = <0x23>, /* UNMAPPED_TX_CHAN */
145 <0x24>, /* CPSW_TX_CHAN */
146 <0x25>, /* SAUL_TX_0_CHAN */
147 <0x26>, /* SAUL_TX_1_CHAN */
148 <0x27>, /* ICSSG_0_TX_CHAN */
149 <0x28>; /* ICSSG_1_TX_CHAN */
150 ti,sci-rm-range-tflow = <0x10>, /* RING_UNMAPPED_TX_CHAN */
151 <0x11>, /* RING_CPSW_TX_CHAN */
152 <0x12>, /* RING_SAUL_TX_0_CHAN */
153 <0x13>, /* RING_SAUL_TX_1_CHAN */
154 <0x14>, /* RING_ICSSG_0_TX_CHAN */
155 <0x15>; /* RING_ICSSG_1_TX_CHAN */
156 ti,sci-rm-range-rchan = <0x29>, /* UNMAPPED_RX_CHAN */
157 <0x2b>, /* CPSW_RX_CHAN */
158 <0x2d>, /* SAUL_RX_0_CHAN */
159 <0x2f>, /* SAUL_RX_1_CHAN */
160 <0x31>, /* SAUL_RX_2_CHAN */
161 <0x33>, /* SAUL_RX_3_CHAN */
162 <0x35>, /* ICSSG_0_RX_CHAN */
163 <0x37>; /* ICSSG_1_RX_CHAN */
164 ti,sci-rm-range-rflow = <0x2a>, /* FLOW_UNMAPPED_RX_CHAN */
165 <0x2c>, /* FLOW_CPSW_RX_CHAN */
166 <0x2e>, /* FLOW_SAUL_RX_0/1_CHAN */
167 <0x32>, /* FLOW_SAUL_RX_2/3_CHAN */
168 <0x36>, /* FLOW_ICSSG_0_RX_CHAN */
169 <0x38>; /* FLOW_ICSSG_1_RX_CHAN */