1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 $id: http://devicetree.org/schemas/dma/st,stm32-dma.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: STMicroelectronics STM32 DMA Controller bindings
10 The STM32 DMA is a general-purpose direct memory access controller capable of
11 supporting 8 independent DMA channels. Each channel can have up to 8 requests.
12 DMA clients connected to the STM32 DMA controller must use the format
13 described in the dma.txt file, using a four-cell specifier for each
14 channel: a phandle to the DMA controller plus the following four integer cells:
16 2. The request line number
17 3. A 32bit mask specifying the DMA channel configuration which are device
19 -bit 9: Peripheral Increment Address
20 0x0: no address increment between transfers
21 0x1: increment address between transfers
22 -bit 10: Memory Increment Address
23 0x0: no address increment between transfers
24 0x1: increment address between transfers
25 -bit 15: Peripheral Increment Offset Size
26 0x0: offset size is linked to the peripheral bus width
27 0x1: offset size is fixed to 4 (32-bit alignment)
28 -bit 16-17: Priority level
33 4. A 32bit bitfield value specifying DMA features which are device dependent:
34 -bit 0-1: DMA FIFO threshold selection
39 -bit 2: DMA direct mode
40 0x0: FIFO mode with threshold selectable with bit 0-1
41 0x1: Direct mode: each DMA request immediately initiates a transfer
42 from/to the memory, FIFO is bypassed.
43 -bit 4: alternative DMA request/acknowledge protocol
44 0x0: Use standard DMA ACK management, where ACK signal is maintained
45 up to the removal of request and transfer completion
46 0x1: Use alternative DMA ACK management, where ACK de-assertion does
47 not wait for the de-assertion of the REQuest, ACK is only managed
48 by transfer completion. This must only be used on channels
49 managing transfers for STM32 USART/UART.
53 - Amelie Delaunay <amelie.delaunay@st.com>
56 - $ref: "dma-controller.yaml#"
73 description: Should contain all of the per-channel DMA
74 interrupts in ascending order with respect to the
81 $ref: /schemas/types.yaml#/definitions/flag
82 description: if defined, it indicates that the controller
83 supports memory-to-memory transfer
91 unevaluatedProperties: false
95 #include <dt-bindings/interrupt-controller/arm-gic.h>
96 #include <dt-bindings/clock/stm32mp1-clks.h>
97 #include <dt-bindings/reset/stm32mp1-resets.h>
98 dma-controller@40026400 {
99 compatible = "st,stm32-dma";
100 reg = <0x40026400 0x400>;
109 clocks = <&clk_hclk>;