Documentation/devicetree/bindings/dma/renesas,rz-dmac.yaml

   1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
   2 %YAML 1.2
   3 ---
   4 $id: http://devicetree.org/schemas/dma/renesas,rz-dmac.yaml#
   5 $schema: http://devicetree.org/meta-schemas/core.yaml#
   6
   7 title: Renesas RZ/G2L DMA Controller
   8
   9 maintainers:
  10   - Biju Das <biju.das.jz@bp.renesas.com>
  11
  12 allOf:
  13   - $ref: "dma-controller.yaml#"
  14
  15 properties:
  16   compatible:
  17     items:
  18       - enum:
  19           - renesas,r9a07g044-dmac # RZ/G2{L,LC}
  20       - const: renesas,rz-dmac
  21
  22   reg:
  23     items:
  24       - description: Control and channel register block
  25       - description: DMA extended resource selector block
  26
  27   interrupts:
  28     maxItems: 17
  29
  30   interrupt-names:
  31     items:
  32       - const: error
  33       - const: ch0
  34       - const: ch1
  35       - const: ch2
  36       - const: ch3
  37       - const: ch4
  38       - const: ch5
  39       - const: ch6
  40       - const: ch7
  41       - const: ch8
  42       - const: ch9
  43       - const: ch10
  44       - const: ch11
  45       - const: ch12
  46       - const: ch13
  47       - const: ch14
  48       - const: ch15
  49
  50   clocks:
  51     items:
  52       - description: DMA main clock
  53       - description: DMA register access clock
  54
  55   '#dma-cells':
  56     const: 1
  57     description:
  58       The cell specifies the encoded MID/RID values of the DMAC port
  59       connected to the DMA client and the slave channel configuration
  60       parameters.
  61       bits[0:9] - Specifies MID/RID value
  62       bit[10] - Specifies DMA request high enable (HIEN)
  63       bit[11] - Specifies DMA request detection type (LVL)
  64       bits[12:14] - Specifies DMAACK output mode (AM)
  65       bit[15] - Specifies Transfer Mode (TM)
  66
  67   dma-channels:
  68     const: 16
  69
  70   power-domains:
  71     maxItems: 1
  72
  73   resets:
  74     items:
  75       - description: Reset for DMA ARESETN reset terminal
  76       - description: Reset for DMA RST_ASYNC reset terminal
  77
  78 required:
  79   - compatible
  80   - reg
  81   - interrupts
  82   - interrupt-names
  83   - clocks
  84   - '#dma-cells'
  85   - dma-channels
  86   - power-domains
  87   - resets
  88
  89 additionalProperties: false
  90
  91 examples:
  92   - |
  93     #include <dt-bindings/interrupt-controller/arm-gic.h>
  94     #include <dt-bindings/clock/r9a07g044-cpg.h>
  95
  96     dmac: dma-controller@11820000 {
  97         compatible = "renesas,r9a07g044-dmac",
  98                      "renesas,rz-dmac";
  99         reg = <0x11820000 0x10000>,
 100               <0x11830000 0x10000>;
 101         interrupts = <GIC_SPI 141 IRQ_TYPE_EDGE_RISING>,
 102                      <GIC_SPI 125 IRQ_TYPE_EDGE_RISING>,
 103                      <GIC_SPI 126 IRQ_TYPE_EDGE_RISING>,
 104                      <GIC_SPI 127 IRQ_TYPE_EDGE_RISING>,
 105                      <GIC_SPI 128 IRQ_TYPE_EDGE_RISING>,
 106                      <GIC_SPI 129 IRQ_TYPE_EDGE_RISING>,
 107                      <GIC_SPI 130 IRQ_TYPE_EDGE_RISING>,
 108                      <GIC_SPI 131 IRQ_TYPE_EDGE_RISING>,
 109                      <GIC_SPI 132 IRQ_TYPE_EDGE_RISING>,
 110                      <GIC_SPI 133 IRQ_TYPE_EDGE_RISING>,
 111                      <GIC_SPI 134 IRQ_TYPE_EDGE_RISING>,
 112                      <GIC_SPI 135 IRQ_TYPE_EDGE_RISING>,
 113                      <GIC_SPI 136 IRQ_TYPE_EDGE_RISING>,
 114                      <GIC_SPI 137 IRQ_TYPE_EDGE_RISING>,
 115                      <GIC_SPI 138 IRQ_TYPE_EDGE_RISING>,
 116                      <GIC_SPI 139 IRQ_TYPE_EDGE_RISING>,
 117                      <GIC_SPI 140 IRQ_TYPE_EDGE_RISING>;
 118         interrupt-names = "error",
 119                           "ch0", "ch1", "ch2", "ch3",
 120                           "ch4", "ch5", "ch6", "ch7",
 121                           "ch8", "ch9", "ch10", "ch11",
 122                           "ch12", "ch13", "ch14", "ch15";
 123         clocks = <&cpg CPG_MOD R9A07G044_DMAC_ACLK>,
 124                  <&cpg CPG_MOD R9A07G044_DMAC_PCLK>;
 125         power-domains = <&cpg>;
 126         resets = <&cpg R9A07G044_DMAC_ARESETN>,
 127                  <&cpg R9A07G044_DMAC_RST_ASYNC>;
 128         #dma-cells = <1>;
 129         dma-channels = <16>;
 130     };