Documentation/devicetree/bindings/dma/altr,msgdma.yaml

   1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
   2 %YAML 1.2
   3 ---
   4 $id: http://devicetree.org/schemas/dma/altr,msgdma.yaml#
   5 $schema: http://devicetree.org/meta-schemas/core.yaml#
   6
   7 title: Altera mSGDMA IP core
   8
   9 maintainers:
  10   - Olivier Dautricourt <olivier.dautricourt@orolia.com>
  11
  12 description: |
  13   Altera / Intel modular Scatter-Gather Direct Memory Access (mSGDMA)
  14   intellectual property (IP)
  15
  16 allOf:
  17   - $ref: "dma-controller.yaml#"
  18
  19 properties:
  20   compatible:
  21     const: altr,socfpga-msgdma
  22
  23   reg:
  24     items:
  25       - description: Control and Status Register Slave Port
  26       - description: Descriptor Slave Port
  27       - description: Response Slave Port
  28
  29   reg-names:
  30     items:
  31       - const: csr
  32       - const: desc
  33       - const: resp
  34
  35   interrupts:
  36     maxItems: 1
  37
  38   "#dma-cells":
  39     const: 1
  40     description:
  41       The cell identifies the channel id (must be 0)
  42
  43 required:
  44   - compatible
  45   - reg
  46   - reg-names
  47   - interrupts
  48
  49 unevaluatedProperties: false
  50
  51 examples:
  52   - |
  53     #include <dt-bindings/interrupt-controller/irq.h>
  54
  55     msgdma_controller: dma-controller@ff200b00 {
  56         compatible = "altr,socfpga-msgdma";
  57         reg = <0xff200b00 0x100>, <0xff200c00 0x100>, <0xff200d00 0x100>;
  58         reg-names = "csr", "desc", "resp";
  59         interrupts = <0 67 IRQ_TYPE_LEVEL_HIGH>;
  60         #dma-cells = <1>;
  61     };