Documentation/devicetree/bindings/display/ti/ti,j721e-dss.yaml

   1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
   2 # Copyright 2019 Texas Instruments Incorporated
   3 %YAML 1.2
   4 ---
   5 $id: "http://devicetree.org/schemas/display/ti/ti,j721e-dss.yaml#"
   6 $schema: "http://devicetree.org/meta-schemas/core.yaml#"
   7
   8 title: Texas Instruments J721E Display Subsystem
   9
  10 maintainers:
  11   - Jyri Sarha <jsarha@ti.com>
  12   - Tomi Valkeinen <tomi.valkeinen@ti.com>
  13
  14 description: |
  15   The J721E TI Keystone Display SubSystem with four output ports and
  16   four video planes. There is two full video planes and two "lite
  17   planes" without scaling support. The video ports can be connected to
  18   the SoC's DPI pins or to integrated display bridges on the SoC.
  19
  20 properties:
  21   compatible:
  22     const: ti,j721e-dss
  23
  24   reg:
  25     items:
  26       - description: common_m DSS Master common
  27       - description: common_s0 DSS Shared common 0
  28       - description: common_s1 DSS Shared common 1
  29       - description: common_s2 DSS Shared common 2
  30       - description: VIDL1 light video plane 1
  31       - description: VIDL2 light video plane 2
  32       - description: VID1 video plane 1
  33       - description: VID1 video plane 2
  34       - description: OVR1 overlay manager for vp1
  35       - description: OVR2 overlay manager for vp2
  36       - description: OVR3 overlay manager for vp3
  37       - description: OVR4 overlay manager for vp4
  38       - description: VP1 video port 1
  39       - description: VP2 video port 2
  40       - description: VP3 video port 3
  41       - description: VP4 video port 4
  42       - description: WB Write Back
  43
  44   reg-names:
  45     items:
  46       - const: common_m
  47       - const: common_s0
  48       - const: common_s1
  49       - const: common_s2
  50       - const: vidl1
  51       - const: vidl2
  52       - const: vid1
  53       - const: vid2
  54       - const: ovr1
  55       - const: ovr2
  56       - const: ovr3
  57       - const: ovr4
  58       - const: vp1
  59       - const: vp2
  60       - const: vp3
  61       - const: vp4
  62       - const: wb
  63
  64   clocks:
  65     items:
  66       - description: fck DSS functional clock
  67       - description: vp1 Video Port 1 pixel clock
  68       - description: vp2 Video Port 2 pixel clock
  69       - description: vp3 Video Port 3 pixel clock
  70       - description: vp4 Video Port 4 pixel clock
  71
  72   clock-names:
  73     items:
  74       - const: fck
  75       - const: vp1
  76       - const: vp2
  77       - const: vp3
  78       - const: vp4
  79
  80   assigned-clocks:
  81     minItems: 1
  82     maxItems: 5
  83
  84   assigned-clock-parents:
  85     minItems: 1
  86     maxItems: 5
  87
  88   interrupts:
  89     items:
  90       - description: common_m DSS Master common
  91       - description: common_s0 DSS Shared common 0
  92       - description: common_s1 DSS Shared common 1
  93       - description: common_s2 DSS Shared common 2
  94
  95   interrupt-names:
  96     items:
  97       - const: common_m
  98       - const: common_s0
  99       - const: common_s1
 100       - const: common_s2
 101
 102   power-domains:
 103     maxItems: 1
 104     description: phandle to the associated power domain
 105
 106   dma-coherent:
 107     type: boolean
 108
 109   ports:
 110     type: object
 111     description:
 112       Ports as described in Documentation/devicetree/bindings/graph.txt
 113     properties:
 114       "#address-cells":
 115         const: 1
 116
 117       "#size-cells":
 118         const: 0
 119
 120       port@0:
 121         type: object
 122         description:
 123           The output port node form video port 1
 124
 125       port@1:
 126         type: object
 127         description:
 128           The output port node from video port 2
 129
 130       port@2:
 131         type: object
 132         description:
 133           The output port node from video port 3
 134
 135       port@3:
 136         type: object
 137         description:
 138           The output port node from video port 4
 139
 140     required:
 141       - "#address-cells"
 142       - "#size-cells"
 143
 144   max-memory-bandwidth:
 145     $ref: /schemas/types.yaml#/definitions/uint32
 146     description:
 147       Input memory (from main memory to dispc) bandwidth limit in
 148       bytes per second
 149
 150 required:
 151   - compatible
 152   - reg
 153   - reg-names
 154   - clocks
 155   - clock-names
 156   - interrupts
 157   - interrupt-names
 158   - ports
 159
 160 additionalProperties: false
 161
 162 examples:
 163   - |
 164     #include <dt-bindings/interrupt-controller/arm-gic.h>
 165     #include <dt-bindings/interrupt-controller/irq.h>
 166     #include <dt-bindings/soc/ti,sci_pm_domain.h>
 167
 168     dss: dss@4a00000 {
 169             compatible = "ti,j721e-dss";
 170             reg =   <0x04a00000 0x10000>, /* common_m */
 171                     <0x04a10000 0x10000>, /* common_s0*/
 172                     <0x04b00000 0x10000>, /* common_s1*/
 173                     <0x04b10000 0x10000>, /* common_s2*/
 174                     <0x04a20000 0x10000>, /* vidl1 */
 175                     <0x04a30000 0x10000>, /* vidl2 */
 176                     <0x04a50000 0x10000>, /* vid1 */
 177                     <0x04a60000 0x10000>, /* vid2 */
 178                     <0x04a70000 0x10000>, /* ovr1 */
 179                     <0x04a90000 0x10000>, /* ovr2 */
 180                     <0x04ab0000 0x10000>, /* ovr3 */
 181                     <0x04ad0000 0x10000>, /* ovr4 */
 182                     <0x04a80000 0x10000>, /* vp1 */
 183                     <0x04aa0000 0x10000>, /* vp2 */
 184                     <0x04ac0000 0x10000>, /* vp3 */
 185                     <0x04ae0000 0x10000>, /* vp4 */
 186                     <0x04af0000 0x10000>; /* wb */
 187             reg-names = "common_m", "common_s0",
 188                     "common_s1", "common_s2",
 189                     "vidl1", "vidl2","vid1","vid2",
 190                     "ovr1", "ovr2", "ovr3", "ovr4",
 191                     "vp1", "vp2", "vp3", "vp4",
 192                     "wb";
 193             clocks =        <&k3_clks 152 0>,
 194                             <&k3_clks 152 1>,
 195                             <&k3_clks 152 4>,
 196                             <&k3_clks 152 9>,
 197                             <&k3_clks 152 13>;
 198             clock-names = "fck", "vp1", "vp2", "vp3", "vp4";
 199             power-domains = <&k3_pds 152 TI_SCI_PD_EXCLUSIVE>;
 200             interrupts =    <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>,
 201                             <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>,
 202                             <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>,
 203                             <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
 204             interrupt-names =       "common_m",
 205                                     "common_s0",
 206                                     "common_s1",
 207                                     "common_s2";
 208             ports {
 209                     #address-cells = <1>;
 210                     #size-cells = <0>;
 211                     port@0 {
 212                             reg = <0>;
 213
 214                             dpi_out_0: endpoint {
 215                                     remote-endpoint = <&dp_bridge_input>;
 216                             };
 217                     };
 218             };
 219     };