Documentation/devicetree/bindings/display/rockchip/rockchip,dw-hdmi.yaml

   1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
   2 %YAML 1.2
   3 ---
   4 $id: http://devicetree.org/schemas/display/rockchip/rockchip,dw-hdmi.yaml#
   5 $schema: http://devicetree.org/meta-schemas/core.yaml#
   6
   7 title: Rockchip DWC HDMI TX Encoder
   8
   9 maintainers:
  10   - Mark Yao <markyao0591@gmail.com>
  11
  12 description: |
  13   The HDMI transmitter is a Synopsys DesignWare HDMI 1.4 TX controller IP
  14   with a companion PHY IP.
  15
  16 allOf:
  17   - $ref: ../bridge/synopsys,dw-hdmi.yaml#
  18
  19 properties:
  20   compatible:
  21     enum:
  22       - rockchip,rk3228-dw-hdmi
  23       - rockchip,rk3288-dw-hdmi
  24       - rockchip,rk3328-dw-hdmi
  25       - rockchip,rk3399-dw-hdmi
  26
  27   reg-io-width:
  28     const: 4
  29
  30   clocks:
  31     minItems: 2
  32     items:
  33       - {}
  34       - {}
  35       # The next three clocks are all optional, but shall be specified in this
  36       # order when present.
  37       - description: The HDMI CEC controller main clock
  38       - description: Power for GRF IO
  39       - description: External clock for some HDMI PHY
  40
  41   clock-names:
  42     minItems: 2
  43     items:
  44       - {}
  45       - {}
  46       - enum:
  47           - cec
  48           - grf
  49           - vpll
  50       - enum:
  51           - grf
  52           - vpll
  53       - const: vpll
  54
  55   ddc-i2c-bus:
  56     $ref: /schemas/types.yaml#/definitions/phandle
  57     description:
  58       The HDMI DDC bus can be connected to either a system I2C master or the
  59       functionally-reduced I2C master contained in the DWC HDMI. When connected
  60       to a system I2C master this property contains a phandle to that I2C
  61       master controller.
  62
  63   phys:
  64     maxItems: 1
  65     description: The HDMI PHY
  66
  67   phy-names:
  68     const: hdmi
  69
  70   pinctrl-names:
  71     description:
  72       The unwedge pinctrl entry shall drive the DDC SDA line low. This is
  73       intended to work around a hardware errata that can cause the DDC I2C
  74       bus to be wedged.
  75     items:
  76       - const: default
  77       - const: unwedge
  78
  79   ports:
  80     $ref: /schemas/graph.yaml#/properties/ports
  81
  82     properties:
  83       port:
  84         $ref: /schemas/graph.yaml#/$defs/port-base
  85         unevaluatedProperties: false
  86         description: Input of the DWC HDMI TX
  87
  88         properties:
  89           endpoint@0:
  90             $ref: /schemas/graph.yaml#/properties/endpoint
  91             description: Connection to the VOPB
  92
  93           endpoint@1:
  94             $ref: /schemas/graph.yaml#/properties/endpoint
  95             description: Connection to the VOPL
  96
  97         required:
  98           - endpoint@0
  99           - endpoint@1
 100
 101     required:
 102       - port
 103
 104   rockchip,grf:
 105     $ref: /schemas/types.yaml#/definitions/phandle
 106     description:
 107       phandle to the GRF to mux vopl/vopb.
 108
 109 required:
 110   - compatible
 111   - reg
 112   - reg-io-width
 113   - clocks
 114   - clock-names
 115   - interrupts
 116   - ports
 117   - rockchip,grf
 118
 119 unevaluatedProperties: false
 120
 121 examples:
 122   - |
 123     #include <dt-bindings/clock/rk3288-cru.h>
 124     #include <dt-bindings/interrupt-controller/arm-gic.h>
 125     #include <dt-bindings/interrupt-controller/irq.h>
 126
 127     hdmi: hdmi@ff980000 {
 128         compatible = "rockchip,rk3288-dw-hdmi";
 129         reg = <0xff980000 0x20000>;
 130         reg-io-width = <4>;
 131         ddc-i2c-bus = <&i2c5>;
 132         rockchip,grf = <&grf>;
 133         interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
 134         clocks = <&cru  PCLK_HDMI_CTRL>, <&cru SCLK_HDMI_HDCP>;
 135         clock-names = "iahb", "isfr";
 136
 137         ports {
 138             port {
 139                 #address-cells = <1>;
 140                 #size-cells = <0>;
 141
 142                 hdmi_in_vopb: endpoint@0 {
 143                     reg = <0>;
 144                     remote-endpoint = <&vopb_out_hdmi>;
 145                 };
 146                 hdmi_in_vopl: endpoint@1 {
 147                     reg = <1>;
 148                     remote-endpoint = <&vopl_out_hdmi>;
 149                 };
 150             };
 151         };
 152     };
 153
 154 ...