1 # SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause
4 $id: http://devicetree.org/schemas/display/msm/dpu-sdm845.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm Display DPU dt properties for SDM845 target
10 - Krishna Manikandan <mkrishn@codeaurora.org>
13 Device tree bindings for MSM Mobile Display Subsystem(MDSS) that encapsulates
14 sub-blocks like DPU display controller, DSI and DP interfaces etc. Device tree
15 bindings of MDSS and DPU are mentioned for SDM845 target.
20 - const: qcom,sdm845-mdss
33 - description: Display AHB clock from gcc
34 - description: Display AXI clock
35 - description: Display core clock
46 interrupt-controller: true
48 "#address-cells": true
57 - description: Phandle to apps_smmu node with SID mask for Hard-Fail port0
58 - description: Phandle to apps_smmu node with SID mask for Hard-Fail port1
63 "^display-controller@[0-9a-f]+$":
65 description: Node containing the properties of DPU.
70 - const: qcom,sdm845-dpu
74 - description: Address offset and size for mdp register set
75 - description: Address offset and size for vbif register set
84 - description: Display ahb clock
85 - description: Display axi clock
86 - description: Display core clock
87 - description: Display vsync clock
102 operating-points-v2: true
104 $ref: /schemas/graph.yaml#/properties/ports
106 Contains the list of output ports from DPU device. These ports
107 connect to interfaces that are external to the DPU hardware,
108 such as DSI, DP etc. Each output port contains an endpoint that
109 describes how it is connected to an external interface.
113 $ref: /schemas/graph.yaml#/properties/port
114 description: DPU_INTF1 (DSI1)
117 $ref: /schemas/graph.yaml#/properties/port
118 description: DPU_INTF2 (DSI2)
131 - operating-points-v2
141 - interrupt-controller
145 additionalProperties: false
149 #include <dt-bindings/clock/qcom,dispcc-sdm845.h>
150 #include <dt-bindings/clock/qcom,gcc-sdm845.h>
151 #include <dt-bindings/interrupt-controller/arm-gic.h>
152 #include <dt-bindings/power/qcom-rpmpd.h>
154 display-subsystem@ae00000 {
155 #address-cells = <1>;
157 compatible = "qcom,sdm845-mdss";
158 reg = <0x0ae00000 0x1000>;
160 power-domains = <&dispcc MDSS_GDSC>;
162 clocks = <&gcc GCC_DISP_AHB_CLK>,
163 <&gcc GCC_DISP_AXI_CLK>,
164 <&dispcc DISP_CC_MDSS_MDP_CLK>;
165 clock-names = "iface", "bus", "core";
167 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
168 interrupt-controller;
169 #interrupt-cells = <1>;
171 iommus = <&apps_smmu 0x880 0x8>,
172 <&apps_smmu 0xc80 0x8>;
175 display-controller@ae01000 {
176 compatible = "qcom,sdm845-dpu";
177 reg = <0x0ae01000 0x8f000>,
179 reg-names = "mdp", "vbif";
181 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
182 <&dispcc DISP_CC_MDSS_AXI_CLK>,
183 <&dispcc DISP_CC_MDSS_MDP_CLK>,
184 <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
185 clock-names = "iface", "bus", "core", "vsync";
187 interrupt-parent = <&mdss>;
189 power-domains = <&rpmhpd SDM845_CX>;
190 operating-points-v2 = <&mdp_opp_table>;
193 #address-cells = <1>;
198 dpu_intf1_out: endpoint {
199 remote-endpoint = <&dsi0_in>;
205 dpu_intf2_out: endpoint {
206 remote-endpoint = <&dsi1_in>;