Documentation/devicetree/bindings/display/msm/dpu-sdm845.yaml

   1 # SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause
   2 %YAML 1.2
   3 ---
   4 $id: http://devicetree.org/schemas/display/msm/dpu-sdm845.yaml#
   5 $schema: http://devicetree.org/meta-schemas/core.yaml#
   6
   7 title: Qualcomm Display DPU dt properties for SDM845 target
   8
   9 maintainers:
  10   - Krishna Manikandan <mkrishn@codeaurora.org>
  11
  12 description: |
  13   Device tree bindings for MSM Mobile Display Subsystem(MDSS) that encapsulates
  14   sub-blocks like DPU display controller, DSI and DP interfaces etc. Device tree
  15   bindings of MDSS and DPU are mentioned for SDM845 target.
  16
  17 properties:
  18   compatible:
  19     items:
  20       - const: qcom,sdm845-mdss
  21
  22   reg:
  23     maxItems: 1
  24
  25   reg-names:
  26     const: mdss
  27
  28   power-domains:
  29     maxItems: 1
  30
  31   clocks:
  32     items:
  33       - description: Display AHB clock from gcc
  34       - description: Display AXI clock
  35       - description: Display core clock
  36
  37   clock-names:
  38     items:
  39       - const: iface
  40       - const: bus
  41       - const: core
  42
  43   interrupts:
  44     maxItems: 1
  45
  46   interrupt-controller: true
  47
  48   "#address-cells": true
  49
  50   "#size-cells": true
  51
  52   "#interrupt-cells":
  53     const: 1
  54
  55   iommus:
  56     items:
  57       - description: Phandle to apps_smmu node with SID mask for Hard-Fail port0
  58       - description: Phandle to apps_smmu node with SID mask for Hard-Fail port1
  59
  60   ranges: true
  61
  62 patternProperties:
  63   "^display-controller@[0-9a-f]+$":
  64     type: object
  65     description: Node containing the properties of DPU.
  66
  67     properties:
  68       compatible:
  69         items:
  70           - const: qcom,sdm845-dpu
  71
  72       reg:
  73         items:
  74           - description: Address offset and size for mdp register set
  75           - description: Address offset and size for vbif register set
  76
  77       reg-names:
  78         items:
  79           - const: mdp
  80           - const: vbif
  81
  82       clocks:
  83         items:
  84           - description: Display ahb clock
  85           - description: Display axi clock
  86           - description: Display core clock
  87           - description: Display vsync clock
  88
  89       clock-names:
  90         items:
  91           - const: iface
  92           - const: bus
  93           - const: core
  94           - const: vsync
  95
  96       interrupts:
  97         maxItems: 1
  98
  99       power-domains:
 100         maxItems: 1
 101
 102       operating-points-v2: true
 103       ports:
 104         $ref: /schemas/graph.yaml#/properties/ports
 105         description: |
 106           Contains the list of output ports from DPU device. These ports
 107           connect to interfaces that are external to the DPU hardware,
 108           such as DSI, DP etc. Each output port contains an endpoint that
 109           describes how it is connected to an external interface.
 110
 111         properties:
 112           port@0:
 113             $ref: /schemas/graph.yaml#/properties/port
 114             description: DPU_INTF1 (DSI1)
 115
 116           port@1:
 117             $ref: /schemas/graph.yaml#/properties/port
 118             description: DPU_INTF2 (DSI2)
 119
 120         required:
 121           - port@0
 122           - port@1
 123
 124     required:
 125       - compatible
 126       - reg
 127       - reg-names
 128       - clocks
 129       - interrupts
 130       - power-domains
 131       - operating-points-v2
 132       - ports
 133
 134 required:
 135   - compatible
 136   - reg
 137   - reg-names
 138   - power-domains
 139   - clocks
 140   - interrupts
 141   - interrupt-controller
 142   - iommus
 143   - ranges
 144
 145 additionalProperties: false
 146
 147 examples:
 148   - |
 149     #include <dt-bindings/clock/qcom,dispcc-sdm845.h>
 150     #include <dt-bindings/clock/qcom,gcc-sdm845.h>
 151     #include <dt-bindings/interrupt-controller/arm-gic.h>
 152     #include <dt-bindings/power/qcom-rpmpd.h>
 153
 154     display-subsystem@ae00000 {
 155           #address-cells = <1>;
 156           #size-cells = <1>;
 157           compatible = "qcom,sdm845-mdss";
 158           reg = <0x0ae00000 0x1000>;
 159           reg-names = "mdss";
 160           power-domains = <&dispcc MDSS_GDSC>;
 161
 162           clocks = <&gcc GCC_DISP_AHB_CLK>,
 163                    <&gcc GCC_DISP_AXI_CLK>,
 164                    <&dispcc DISP_CC_MDSS_MDP_CLK>;
 165           clock-names = "iface", "bus", "core";
 166
 167           interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
 168           interrupt-controller;
 169           #interrupt-cells = <1>;
 170
 171           iommus = <&apps_smmu 0x880 0x8>,
 172                    <&apps_smmu 0xc80 0x8>;
 173           ranges;
 174
 175           display-controller@ae01000 {
 176                     compatible = "qcom,sdm845-dpu";
 177                     reg = <0x0ae01000 0x8f000>,
 178                           <0x0aeb0000 0x2008>;
 179                     reg-names = "mdp", "vbif";
 180
 181                     clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
 182                              <&dispcc DISP_CC_MDSS_AXI_CLK>,
 183                              <&dispcc DISP_CC_MDSS_MDP_CLK>,
 184                              <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
 185                     clock-names = "iface", "bus", "core", "vsync";
 186
 187                     interrupt-parent = <&mdss>;
 188                     interrupts = <0>;
 189                     power-domains = <&rpmhpd SDM845_CX>;
 190                     operating-points-v2 = <&mdp_opp_table>;
 191
 192                     ports {
 193                            #address-cells = <1>;
 194                            #size-cells = <0>;
 195
 196                            port@0 {
 197                                    reg = <0>;
 198                                    dpu_intf1_out: endpoint {
 199                                                   remote-endpoint = <&dsi0_in>;
 200                                    };
 201                            };
 202
 203                            port@1 {
 204                                    reg = <1>;
 205                                    dpu_intf2_out: endpoint {
 206                                                   remote-endpoint = <&dsi1_in>;
 207                                    };
 208                            };
 209                     };
 210           };
 211     };
 212 ...