Documentation/devicetree/bindings/display/msm/dpu-sc7180.yaml

   1 # SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause
   2 %YAML 1.2
   3 ---
   4 $id: http://devicetree.org/schemas/display/msm/dpu-sc7180.yaml#
   5 $schema: http://devicetree.org/meta-schemas/core.yaml#
   6
   7 title: Qualcomm Display DPU dt properties for SC7180 target
   8
   9 maintainers:
  10   - Krishna Manikandan <mkrishn@codeaurora.org>
  11
  12 description: |
  13   Device tree bindings for MSM Mobile Display Subsystem(MDSS) that encapsulates
  14   sub-blocks like DPU display controller, DSI and DP interfaces etc. Device tree
  15   bindings of MDSS and DPU are mentioned for SC7180 target.
  16
  17 properties:
  18   compatible:
  19     items:
  20       - const: qcom,sc7180-mdss
  21
  22   reg:
  23     maxItems: 1
  24
  25   reg-names:
  26     const: mdss
  27
  28   power-domains:
  29     maxItems: 1
  30
  31   clocks:
  32     items:
  33       - description: Display AHB clock from gcc
  34       - description: Display AHB clock from dispcc
  35       - description: Display core clock
  36
  37   clock-names:
  38     items:
  39       - const: iface
  40       - const: ahb
  41       - const: core
  42
  43   interrupts:
  44     maxItems: 1
  45
  46   interrupt-controller: true
  47
  48   "#address-cells": true
  49
  50   "#size-cells": true
  51
  52   "#interrupt-cells":
  53     const: 1
  54
  55   iommus:
  56     items:
  57       - description: Phandle to apps_smmu node with SID mask for Hard-Fail port0
  58
  59   ranges: true
  60
  61   interconnects:
  62     items:
  63       - description: Interconnect path specifying the port ids for data bus
  64
  65   interconnect-names:
  66     const: mdp0-mem
  67
  68 patternProperties:
  69   "^display-controller@[0-9a-f]+$":
  70     type: object
  71     description: Node containing the properties of DPU.
  72
  73     properties:
  74       compatible:
  75         items:
  76           - const: qcom,sc7180-dpu
  77
  78       reg:
  79         items:
  80           - description: Address offset and size for mdp register set
  81           - description: Address offset and size for vbif register set
  82
  83       reg-names:
  84         items:
  85           - const: mdp
  86           - const: vbif
  87
  88       clocks:
  89         items:
  90           - description: Display hf axi clock
  91           - description: Display ahb clock
  92           - description: Display rotator clock
  93           - description: Display lut clock
  94           - description: Display core clock
  95           - description: Display vsync clock
  96
  97       clock-names:
  98         items:
  99           - const: bus
 100           - const: iface
 101           - const: rot
 102           - const: lut
 103           - const: core
 104           - const: vsync
 105
 106       interrupts:
 107         maxItems: 1
 108
 109       power-domains:
 110         maxItems: 1
 111
 112       operating-points-v2: true
 113
 114       ports:
 115         $ref: /schemas/graph.yaml#/properties/ports
 116         description: |
 117           Contains the list of output ports from DPU device. These ports
 118           connect to interfaces that are external to the DPU hardware,
 119           such as DSI, DP etc. Each output port contains an endpoint that
 120           describes how it is connected to an external interface.
 121
 122         properties:
 123           port@0:
 124             $ref: /schemas/graph.yaml#/properties/port
 125             description: DPU_INTF1 (DSI1)
 126
 127           port@2:
 128             $ref: /schemas/graph.yaml#/properties/port
 129             description: DPU_INTF0 (DP)
 130
 131         required:
 132           - port@0
 133
 134     required:
 135       - compatible
 136       - reg
 137       - reg-names
 138       - clocks
 139       - interrupts
 140       - power-domains
 141       - operating-points-v2
 142       - ports
 143
 144 required:
 145   - compatible
 146   - reg
 147   - reg-names
 148   - power-domains
 149   - clocks
 150   - interrupts
 151   - interrupt-controller
 152   - iommus
 153   - ranges
 154
 155 additionalProperties: false
 156
 157 examples:
 158   - |
 159     #include <dt-bindings/clock/qcom,dispcc-sc7180.h>
 160     #include <dt-bindings/clock/qcom,gcc-sc7180.h>
 161     #include <dt-bindings/interrupt-controller/arm-gic.h>
 162     #include <dt-bindings/interconnect/qcom,sdm845.h>
 163     #include <dt-bindings/power/qcom-rpmpd.h>
 164
 165     display-subsystem@ae00000 {
 166          #address-cells = <1>;
 167          #size-cells = <1>;
 168          compatible = "qcom,sc7180-mdss";
 169          reg = <0xae00000 0x1000>;
 170          reg-names = "mdss";
 171          power-domains = <&dispcc MDSS_GDSC>;
 172          clocks = <&gcc GCC_DISP_AHB_CLK>,
 173                   <&dispcc DISP_CC_MDSS_AHB_CLK>,
 174                   <&dispcc DISP_CC_MDSS_MDP_CLK>;
 175          clock-names = "iface", "ahb", "core";
 176
 177          interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
 178          interrupt-controller;
 179          #interrupt-cells = <1>;
 180
 181          interconnects = <&mmss_noc MASTER_MDP0 &mc_virt SLAVE_EBI1>;
 182          interconnect-names = "mdp0-mem";
 183
 184          iommus = <&apps_smmu 0x800 0x2>;
 185          ranges;
 186
 187          display-controller@ae01000 {
 188                    compatible = "qcom,sc7180-dpu";
 189                    reg = <0x0ae01000 0x8f000>,
 190                          <0x0aeb0000 0x2008>;
 191
 192                    reg-names = "mdp", "vbif";
 193
 194                    clocks = <&gcc GCC_DISP_HF_AXI_CLK>,
 195                             <&dispcc DISP_CC_MDSS_AHB_CLK>,
 196                             <&dispcc DISP_CC_MDSS_ROT_CLK>,
 197                             <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>,
 198                             <&dispcc DISP_CC_MDSS_MDP_CLK>,
 199                             <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
 200                    clock-names = "bus", "iface", "rot", "lut", "core",
 201                                  "vsync";
 202
 203                    interrupt-parent = <&mdss>;
 204                    interrupts = <0>;
 205                    power-domains = <&rpmhpd SC7180_CX>;
 206                    operating-points-v2 = <&mdp_opp_table>;
 207
 208                    ports {
 209                            #address-cells = <1>;
 210                            #size-cells = <0>;
 211
 212                            port@0 {
 213                                    reg = <0>;
 214                                    dpu_intf1_out: endpoint {
 215                                                   remote-endpoint = <&dsi0_in>;
 216                                    };
 217                            };
 218
 219                             port@2 {
 220                                     reg = <2>;
 221                                     dpu_intf0_out: endpoint {
 222                                                    remote-endpoint = <&dp_in>;
 223                                     };
 224                             };
 225                    };
 226          };
 227     };
 228 ...