1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 $id: http://devicetree.org/schemas/display/mediatek/mediatek,hdmi.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Mediatek HDMI Encoder Device Tree Bindings
10 - CK Hu <ck.hu@mediatek.com>
11 - Jitao shi <jitao.shi@mediatek.com>
14 The Mediatek HDMI encoder can generate HDMI 1.4a or MHL 2.0 signals from
20 - mediatek,mt2701-hdmi
21 - mediatek,mt7623-hdmi
22 - mediatek,mt8167-hdmi
23 - mediatek,mt8173-hdmi
33 - description: Pixel Clock
34 - description: HDMI PLL
35 - description: Bit Clock
36 - description: S/PDIF Clock
53 $ref: '/schemas/types.yaml#/definitions/phandle-array'
56 phandle link and register offset to the system configuration registers.
59 $ref: /schemas/graph.yaml#/properties/ports
63 $ref: /schemas/graph.yaml#/properties/port
65 Input port node. This port should be connected to a DPI output port.
68 $ref: /schemas/graph.yaml#/properties/port
70 Output port node. This port should be connected to the input port of a connector
71 node that contains a ddc-i2c-bus property, or to the input port of an attached
72 bridge chip, such as a SlimPort transmitter.
86 - mediatek,syscon-hdmi
89 additionalProperties: false
93 #include <dt-bindings/clock/mt8173-clk.h>
94 #include <dt-bindings/interrupt-controller/arm-gic.h>
95 #include <dt-bindings/interrupt-controller/irq.h>
96 hdmi0: hdmi@14025000 {
97 compatible = "mediatek,mt8173-hdmi";
98 reg = <0x14025000 0x400>;
99 interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_LOW>;
100 clocks = <&mmsys CLK_MM_HDMI_PIXEL>,
101 <&mmsys CLK_MM_HDMI_PLLCK>,
102 <&mmsys CLK_MM_HDMI_AUDIO>,
103 <&mmsys CLK_MM_HDMI_SPDIF>;
104 clock-names = "pixel", "pll", "bclk", "spdif";
105 pinctrl-names = "default";
106 pinctrl-0 = <&hdmi_pin>;
109 mediatek,syscon-hdmi = <&mmsys 0x900>;
112 #address-cells = <1>;
119 remote-endpoint = <&dpi0_out>;
126 hdmi0_out: endpoint {
127 remote-endpoint = <&hdmi_con_in>;