1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 $id: http://devicetree.org/schemas/clock/samsung,exynos-audss-clock.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Samsung Exynos SoC Audio SubSystem clock controller
10 - Chanwoo Choi <cw00.choi@samsung.com>
11 - Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
12 - Sylwester Nawrocki <s.nawrocki@samsung.com>
13 - Tomasz Figa <tomasz.figa@gmail.com>
16 All available clocks are defined as preprocessor macros in
17 include/dt-bindings/clock/exynos-audss-clk.h header.
22 - samsung,exynos4210-audss-clock
23 - samsung,exynos5250-audss-clock
24 - samsung,exynos5410-audss-clock
25 - samsung,exynos5420-audss-clock
31 Fixed rate PLL reference clock, parent of mout_audss. "fin_pll" is
32 used if not specified.
34 Input PLL to the AudioSS block, parent of mout_audss. "fout_epll" is
35 used if not specified.
37 Audio bus clock, parent of mout_i2s. "sclk_audio0" is used if not
40 PCM clock, parent of sclk_pcm. "sclk_pcm0" is used if not specified.
42 External i2s clock, parent of mout_i2s. "cdclk0" is used if not
70 additionalProperties: false
74 clock-controller@3810000 {
75 compatible = "samsung,exynos5250-audss-clock";
76 reg = <0x03810000 0x0c>;
78 clocks = <&clock 1>, <&clock 7>, <&clock 138>, <&clock 160>, <&ext_i2s_clk>;
79 clock-names = "pll_ref", "pll_in", "sclk_audio", "sclk_pcm_in", "cdclk";