Documentation/devicetree/bindings/bus/intel,ixp4xx-expansion-bus-controller.yaml

   1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
   2 %YAML 1.2
   3 ---
   4 $id: http://devicetree.org/schemas/bus/intel,ixp4xx-expansion-bus-controller.yaml#
   5 $schema: http://devicetree.org/meta-schemas/core.yaml#
   6
   7 title: Intel IXP4xx Expansion Bus Controller
   8
   9 description: |
  10   The IXP4xx expansion bus controller handles access to devices on the
  11   memory-mapped expansion bus on the Intel IXP4xx family of system on chips,
  12   including IXP42x, IXP43x, IXP45x and IXP46x.
  13
  14 maintainers:
  15   - Linus Walleij <linus.walleij@linaro.org>
  16
  17 properties:
  18   $nodename:
  19     pattern: '^bus@[0-9a-f]+$'
  20
  21   compatible:
  22     items:
  23       - enum:
  24           - intel,ixp42x-expansion-bus-controller
  25           - intel,ixp43x-expansion-bus-controller
  26           - intel,ixp45x-expansion-bus-controller
  27           - intel,ixp46x-expansion-bus-controller
  28       - const: syscon
  29
  30   reg:
  31     description: Control registers for the expansion bus, these are not
  32       inside the memory range handled by the expansion bus.
  33     maxItems: 1
  34
  35   native-endian:
  36     $ref: /schemas/types.yaml#/definitions/flag
  37     description: The IXP4xx has a peculiar MMIO access scheme, as it changes
  38       the access pattern for words (swizzling) on the bus depending on whether
  39       the SoC is running in big-endian or little-endian mode. Thus the
  40       registers must always be accessed using native endianness.
  41
  42   "#address-cells":
  43     description: |
  44       The first cell is the chip select number.
  45       The second cell is the address offset within the bank.
  46     const: 2
  47
  48   "#size-cells":
  49     const: 1
  50
  51   ranges: true
  52   dma-ranges: true
  53
  54 patternProperties:
  55   "^.*@[0-7],[0-9a-f]+$":
  56     description: Devices attached to chip selects are represented as
  57       subnodes.
  58     type: object
  59
  60     properties:
  61       intel,ixp4xx-eb-t1:
  62         description: Address timing, extend address phase with n cycles.
  63         $ref: /schemas/types.yaml#/definitions/uint32
  64         maximum: 3
  65
  66       intel,ixp4xx-eb-t2:
  67         description: Setup chip select timing, extend setup phase with n cycles.
  68         $ref: /schemas/types.yaml#/definitions/uint32
  69         maximum: 3
  70
  71       intel,ixp4xx-eb-t3:
  72         description: Strobe timing, extend strobe phase with n cycles.
  73         $ref: /schemas/types.yaml#/definitions/uint32
  74         maximum: 15
  75
  76       intel,ixp4xx-eb-t4:
  77         description: Hold timing, extend hold phase with n cycles.
  78         $ref: /schemas/types.yaml#/definitions/uint32
  79         maximum: 3
  80
  81       intel,ixp4xx-eb-t5:
  82         description: Recovery timing, extend recovery phase with n cycles.
  83         $ref: /schemas/types.yaml#/definitions/uint32
  84         maximum: 15
  85
  86       intel,ixp4xx-eb-cycle-type:
  87         description: The type of cycles to use on the expansion bus for this
  88           chip select. 0 = Intel cycles, 1 = Motorola cycles, 2 = HPI cycles.
  89         $ref: /schemas/types.yaml#/definitions/uint32
  90         enum: [0, 1, 2]
  91
  92       intel,ixp4xx-eb-byte-access-on-halfword:
  93         description: Allow byte read access on half word devices.
  94         $ref: /schemas/types.yaml#/definitions/uint32
  95         enum: [0, 1]
  96
  97       intel,ixp4xx-eb-hpi-hrdy-pol-high:
  98         description: Set HPI HRDY polarity to active high when using HPI.
  99         $ref: /schemas/types.yaml#/definitions/uint32
 100         enum: [0, 1]
 101
 102       intel,ixp4xx-eb-mux-address-and-data:
 103         description: Multiplex address and data on the data bus.
 104         $ref: /schemas/types.yaml#/definitions/uint32
 105         enum: [0, 1]
 106
 107       intel,ixp4xx-eb-ahb-split-transfers:
 108         description: Enable AHB split transfers.
 109         $ref: /schemas/types.yaml#/definitions/uint32
 110         enum: [0, 1]
 111
 112       intel,ixp4xx-eb-write-enable:
 113         description: Enable write cycles.
 114         $ref: /schemas/types.yaml#/definitions/uint32
 115         enum: [0, 1]
 116
 117       intel,ixp4xx-eb-byte-access:
 118         description: Expansion bus uses only 8 bits. The default is to use
 119           16 bits.
 120         $ref: /schemas/types.yaml#/definitions/uint32
 121         enum: [0, 1]
 122
 123 required:
 124   - compatible
 125   - reg
 126   - native-endian
 127   - "#address-cells"
 128   - "#size-cells"
 129   - ranges
 130   - dma-ranges
 131
 132 additionalProperties: false
 133
 134 examples:
 135   - |
 136     #include <dt-bindings/interrupt-controller/irq.h>
 137     bus@50000000 {
 138         compatible = "intel,ixp42x-expansion-bus-controller", "syscon";
 139         reg = <0xc4000000 0x28>;
 140         native-endian;
 141         #address-cells = <2>;
 142         #size-cells = <1>;
 143         ranges = <0 0x0 0x50000000 0x01000000>,
 144                  <1 0x0 0x51000000 0x01000000>;
 145         dma-ranges = <0 0x0 0x50000000 0x01000000>,
 146                      <1 0x0 0x51000000 0x01000000>;
 147         flash@0,0 {
 148             compatible = "intel,ixp4xx-flash", "cfi-flash";
 149             bank-width = <2>;
 150             reg = <0 0x00000000 0x1000000>;
 151             intel,ixp4xx-eb-t3 = <3>;
 152             intel,ixp4xx-eb-cycle-type = <0>;
 153             intel,ixp4xx-eb-byte-access-on-halfword = <1>;
 154             intel,ixp4xx-eb-write-enable = <1>;
 155             intel,ixp4xx-eb-byte-access = <0>;
 156         };
 157         serial@1,0 {
 158             compatible = "exar,xr16l2551", "ns8250";
 159             reg = <1 0x00000000 0x10>;
 160             interrupt-parent = <&gpio0>;
 161             interrupts = <4 IRQ_TYPE_LEVEL_LOW>;
 162             clock-frequency = <1843200>;
 163             intel,ixp4xx-eb-t3 = <3>;
 164             intel,ixp4xx-eb-cycle-type = <1>;
 165             intel,ixp4xx-eb-write-enable = <1>;
 166             intel,ixp4xx-eb-byte-access = <1>;
 167         };
 168     };