1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 $id: http://devicetree.org/schemas/bus/intel,ixp4xx-expansion-bus-controller.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Intel IXP4xx Expansion Bus Controller
10 The IXP4xx expansion bus controller handles access to devices on the
11 memory-mapped expansion bus on the Intel IXP4xx family of system on chips,
12 including IXP42x, IXP43x, IXP45x and IXP46x.
15 - Linus Walleij <linus.walleij@linaro.org>
19 pattern: '^bus@[0-9a-f]+$'
24 - intel,ixp42x-expansion-bus-controller
25 - intel,ixp43x-expansion-bus-controller
26 - intel,ixp45x-expansion-bus-controller
27 - intel,ixp46x-expansion-bus-controller
31 description: Control registers for the expansion bus, these are not
32 inside the memory range handled by the expansion bus.
36 $ref: /schemas/types.yaml#/definitions/flag
37 description: The IXP4xx has a peculiar MMIO access scheme, as it changes
38 the access pattern for words (swizzling) on the bus depending on whether
39 the SoC is running in big-endian or little-endian mode. Thus the
40 registers must always be accessed using native endianness.
44 The first cell is the chip select number.
45 The second cell is the address offset within the bank.
55 "^.*@[0-7],[0-9a-f]+$":
56 description: Devices attached to chip selects are represented as
62 description: Address timing, extend address phase with n cycles.
63 $ref: /schemas/types.yaml#/definitions/uint32
67 description: Setup chip select timing, extend setup phase with n cycles.
68 $ref: /schemas/types.yaml#/definitions/uint32
72 description: Strobe timing, extend strobe phase with n cycles.
73 $ref: /schemas/types.yaml#/definitions/uint32
77 description: Hold timing, extend hold phase with n cycles.
78 $ref: /schemas/types.yaml#/definitions/uint32
82 description: Recovery timing, extend recovery phase with n cycles.
83 $ref: /schemas/types.yaml#/definitions/uint32
86 intel,ixp4xx-eb-cycle-type:
87 description: The type of cycles to use on the expansion bus for this
88 chip select. 0 = Intel cycles, 1 = Motorola cycles, 2 = HPI cycles.
89 $ref: /schemas/types.yaml#/definitions/uint32
92 intel,ixp4xx-eb-byte-access-on-halfword:
93 description: Allow byte read access on half word devices.
94 $ref: /schemas/types.yaml#/definitions/uint32
97 intel,ixp4xx-eb-hpi-hrdy-pol-high:
98 description: Set HPI HRDY polarity to active high when using HPI.
99 $ref: /schemas/types.yaml#/definitions/uint32
102 intel,ixp4xx-eb-mux-address-and-data:
103 description: Multiplex address and data on the data bus.
104 $ref: /schemas/types.yaml#/definitions/uint32
107 intel,ixp4xx-eb-ahb-split-transfers:
108 description: Enable AHB split transfers.
109 $ref: /schemas/types.yaml#/definitions/uint32
112 intel,ixp4xx-eb-write-enable:
113 description: Enable write cycles.
114 $ref: /schemas/types.yaml#/definitions/uint32
117 intel,ixp4xx-eb-byte-access:
118 description: Expansion bus uses only 8 bits. The default is to use
120 $ref: /schemas/types.yaml#/definitions/uint32
132 additionalProperties: false
136 #include <dt-bindings/interrupt-controller/irq.h>
138 compatible = "intel,ixp42x-expansion-bus-controller", "syscon";
139 reg = <0xc4000000 0x28>;
141 #address-cells = <2>;
143 ranges = <0 0x0 0x50000000 0x01000000>,
144 <1 0x0 0x51000000 0x01000000>;
145 dma-ranges = <0 0x0 0x50000000 0x01000000>,
146 <1 0x0 0x51000000 0x01000000>;
148 compatible = "intel,ixp4xx-flash", "cfi-flash";
150 reg = <0 0x00000000 0x1000000>;
151 intel,ixp4xx-eb-t3 = <3>;
152 intel,ixp4xx-eb-cycle-type = <0>;
153 intel,ixp4xx-eb-byte-access-on-halfword = <1>;
154 intel,ixp4xx-eb-write-enable = <1>;
155 intel,ixp4xx-eb-byte-access = <0>;
158 compatible = "exar,xr16l2551", "ns8250";
159 reg = <1 0x00000000 0x10>;
160 interrupt-parent = <&gpio0>;
161 interrupts = <4 IRQ_TYPE_LEVEL_LOW>;
162 clock-frequency = <1843200>;
163 intel,ixp4xx-eb-t3 = <3>;
164 intel,ixp4xx-eb-cycle-type = <1>;
165 intel,ixp4xx-eb-write-enable = <1>;
166 intel,ixp4xx-eb-byte-access = <1>;