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drm/i915/rkl: Add DP vswing programming tables
2021-01-06 Matt Roperdrm/i915/rkl: Add DP vswing programming tables
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
...msgid/20201218040535.45492-1-matthew.d.roper@intel.com
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2020-11-17 Bob Paauwedrm/i915: Tweaked Wa_14010685332 for PCHs used on gen11...
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
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2020-10-16 Matt Roperdrm/i915/rkl: Add new cdclk table
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
...msgid/20201015220038.271740-1-matthew.d.roper@intel.com
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2020-10-10 Matt Roperdrm/i915: Update gen12 multicast register ranges
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
...msgid/20201009194442.3668677-4-matthew.d.roper@intel.com
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2020-10-10 Matt Roperdrm/i915: Update gen12 forcewake table
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
...msgid/20201009194442.3668677-3-matthew.d.roper@intel.com
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2020-10-10 Matt Roperdrm/i915: Rename FORCEWAKE_BLITTER to FORCEWAKE_GT
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
...msgid/20201009194442.3668677-2-matthew.d.roper@intel.com
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2020-06-26 Matt Roperdrm/i915: Extend Wa_14010685332 to all ICP+ PCH's
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
...msgid/20200617180006.4130501-1-matthew.d.roper@intel.com
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2020-06-09 Aditya Swarupdrm/i915/rkl: Don't try to read out DSI transcoders
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
...msgid/20200606025740.3308880-5-matthew.d.roper@intel.com
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2020-06-09 Matt Roperdrm/i915/rkl: Update TGP's pin mapping when paired...
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
...msgid/20200606025740.3308880-4-matthew.d.roper@intel.com
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2020-06-09 Matt Roperdrm/i915/rkl: RKL uses ABOX0 for pixel transfers
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
...msgid/20200606025740.3308880-2-matthew.d.roper@intel.com
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2020-06-04 José Roberto de... drm/i915/rkl: Disable PSR2
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
...msgid/20200603211529.3005059-15-matthew.d.roper@intel.com
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2020-06-04 Matt Roperdrm/i915/rkl: Don't try to access transcoder D
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
...msgid/20200603211529.3005059-10-matthew.d.roper@intel.com
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2020-06-04 Matt Roperdrm/i915/rkl: Setup ports/phys
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
...msgid/20200603211529.3005059-6-matthew.d.roper@intel.com
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2020-06-04 Matt Roperdrm/i915/rkl: Handle comp master/slave relationships...
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
...msgid/20200603211529.3005059-12-matthew.d.roper@intel.com
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2020-06-04 Matt Roperdrm/i915/rkl: Add DDC pin mapping
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
...msgid/20200603211529.3005059-9-matthew.d.roper@intel.com
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2020-06-04 Lucas De Marchidrm/i915/rkl: provide port/phy mapping for vbt
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
...msgid/20200603211529.3005059-7-matthew.d.roper@intel.com
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2020-06-04 Matt Roperdrm/i915/rkl: Set transcoder mask properly
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
...msgid/20200603211529.3005059-2-matthew.d.roper@intel.com
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2020-05-05 Matt Roperdrm/i915/icp: Add Wa_14010685332
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
...msgid/20200501213701.371443-1-matthew.d.roper@intel.com
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2020-04-27 Matt Roperdrm/i915: Use proper fault mask in interrupt postinstall too
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
...msgid/20200424231423.4065231-1-matthew.d.roper@intel.com
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2020-04-21 Matt Roperdrm/i915: Use single set of AUX powerwell ops for gen11+
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
...msgid/20200415233435.3064257-2-matthew.d.roper@intel.com
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2020-04-17 Matt Roperdrm/i915/tgl: TBT AUX should use TC power well ops
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
...msgid/20200415233435.3064257-1-matthew.d.roper@intel.com
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2020-04-15 Matt Roperdrm/i915/tgl: Initialize multicast register steering...
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
...msgid/20200414211118.2787489-4-matthew.d.roper@intel.com
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2020-04-15 Matt Roperdrm/i915/tgl: Extend Wa_1409767108:tgl to B0 stepping
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
...msgid/20200414211118.2787489-2-matthew.d.roper@intel.com
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2020-04-15 Matt Roperdrm/i915/tgl: Add Wa_14010477008:tgl
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
...msgid/20200414211118.2787489-3-matthew.d.roper@intel.com
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2020-04-15 Matt Atwooddrm/i915/ehl: extended Wa_2006604312 to ehl
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
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2020-04-02 Swathi Dhanavanthridrm/i915/tgl: Make Wa_14010229206 permanent
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
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2020-03-19 Swathi Dhanavanthridrm/i915/tgl: Add new PCI IDs to TGL
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
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2020-03-13 Matt Roperdrm/i915: Add Wa_1605460711 / Wa_1408767742 to ICL...
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
...msgid/20200311162300.1838847-7-matthew.d.roper@intel.com
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2020-03-13 Matt Roperdrm/i915: Apply Wa_1406680159:icl,ehl as an engine...
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
...msgid/20200311162300.1838847-6-matthew.d.roper@intel.com
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2020-03-13 Matt Roperdrm/i915: Add Wa_1406306137:icl,ehl
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
...msgid/20200311162300.1838847-5-matthew.d.roper@intel.com
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2020-03-13 Matt Roperdrm/i915: Add Wa_1604278689:icl,ehl
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
...msgid/20200311162300.1838847-4-matthew.d.roper@intel.com
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2020-03-13 Matt Roperdrm/i915: Add Wa_1209644611:icl,ehl
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
...msgid/20200311162300.1838847-3-matthew.d.roper@intel.com
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2020-03-13 Matt Roperdrm/i915: Handle all MCR ranges
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
...msgid/20200311162300.1838847-2-matthew.d.roper@intel.com
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2020-03-09 Matt Roperdrm/i915/tgl: Don't treat unslice registers as masked
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
...msgid/20200306171139.1414649-1-matthew.d.roper@intel.com
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2020-03-04 Matt Roperdrm/i915/ehl: Check PHY type before reading DPLL frequency
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
...msgid/20200303195043.959913-1-matthew.d.roper@intel.com
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2020-02-26 Matt Atwooddrm/i915/tgl: Add Wa_1606054188:tgl
Cc: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
...msgid/20200224223651.3801646-1-matthew.d.roper@intel.com
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2020-02-26 Matt Roperdrm/i915/tgl: Allow DC5/DC6 entry while PG2 is active
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
...msgid/20200220231843.3127468-1-matthew.d.roper@intel.com
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2020-02-21 Matt Roperdrm/i915/tgl: Add Wa_22010178259:tgl
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
...msgid/20200219215655.2923650-1-matthew.d.roper@intel.com
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2020-02-20 Matt Roperdrm/i915/tgl: Program MBUS_ABOX{1,2}_CTL during display...
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
...msgid/20200204011032.582737-2-matthew.d.roper@intel.com
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2020-02-20 Matt Roperdrm/i915: Program MBUS with rmw during initialization
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
...msgid/20200204011032.582737-1-matthew.d.roper@intel.com
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2020-02-18 Rafael Antognollidrm/i915/tgl: Add Wa_1808121037 to tgl.
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
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2020-02-10 Matt Roperdrm/i915/tgl: Update cdclk voltage level settings
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
...msgid/20200207001417.1229251-2-matthew.d.roper@intel.com
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2020-02-10 Matt Roperdrm/i915/ehl: Update port clock voltage level requirements
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
...msgid/20200207001417.1229251-1-matthew.d.roper@intel.com
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2020-01-16 Matt Atwooddrm/i915: add Wa_14010594013: icl,ehl
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
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2020-01-15 Radhakrishna Sripadadrm/i915/tgl: Add Wa_1409825376 to tgl
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
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2020-01-14 Matt Roperdrm/i915/gen11: Add additional pcode status values
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
...msgid/20200111014511.2988923-1-matthew.d.roper@intel.com
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2020-01-10 Vivek Kasireddydrm/i915/dsi: Parse the I2C element from the VBT MIPI...
Cc: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
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2020-01-06 Kai Vehmanendrm/i915: Limit audio CDCLK>=2*BCLK constraint back...
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
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2020-01-01 Matt Roperdrm/i915: Add Wa_1407352427:icl,ehl
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
...msgid/20191231190713.1549533-1-matthew.d.roper@intel.com
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2019-12-31 Matt Roperdrm/i915/tgl: Assume future platforms will inherit...
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
...msgid/20191224231521.3430660-1-matthew.d.roper@intel.com
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2019-12-27 Matt Roperdrm/i915/tgl: Extend Wa_1408615072 to tgl
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
...msgid/20191224012026.3157766-4-matthew.d.roper@intel.com
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2019-12-27 Matt Roperdrm/i915: Add Wa_1408615072 and Wa_1407596294 to icl,ehl
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
...msgid/20191224012026.3157766-3-matthew.d.roper@intel.com
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2019-12-27 Matt Roperdrm/i915: Extend WaDisableDARBFClkGating to icl,ehl,tgl
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
...msgid/20191224012026.3157766-2-matthew.d.roper@intel.com
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2019-12-13 Matt Roperdrm/i915/icl: Cleanup combo PHY aux power well handlers
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
...msgid/20191213010600.701315-1-matthew.d.roper@intel.com
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2019-12-13 Matt Roperdrm/i915/tgl: Drop Wa#1178
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
...msgid/20191213001511.678070-3-matthew.d.roper@intel.com
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2019-12-13 Matt Roperdrm/i915/ehl: Define EHL powerwells independently of ICL
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
...msgid/20191213001511.678070-2-matthew.d.roper@intel.com
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2019-12-10 Matt Roperdrm/i915/tgl: Program BW_BUDDY registers during display...
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
...msgid/20191205224848.76712-1-matthew.d.roper@intel.com
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2019-12-03 Matt Roperdrm/i915/irq: Refactor gen11 display interrupt handling
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
...msgid/20191202171608.3361125-1-matthew.d.roper@intel.com
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2019-12-02 Matt Roperdrm/i915: Program SHPD_FILTER_CNT on CNP+
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
...msgid/20191127221314.575575-3-matthew.d.roper@intel.com
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2019-12-02 Matt Roperdrm/i915/ehl: Make icp_digital_port_connected() use...
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
...msgid/20191127221314.575575-2-matthew.d.roper@intel.com
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2019-12-02 Matt Roperdrm/i915: Handle SDEISR according to PCH rather than...
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
...msgid/20191127221314.575575-1-matthew.d.roper@intel.com
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2019-11-27 Kai Vehmanendrm/i915/dp: fix DP audio for PORT_A on gen12+
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
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2019-11-19 Matt Roperdrm/i915/tgl: Add DKL PHY vswing table for HDMI
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
...msgid/20191118180219.9309-1-matthew.d.roper@intel.com
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2019-11-19 Matt Roperdrm/i915/ehl: Update voltage level checks
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
...msgid/20191118164412.26216-1-matthew.d.roper@intel.com
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2019-11-18 Matt Roperdrm/i915/vbt: Handle generic DTD block
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
...msgid/20191115165132.9472-3-matthew.d.roper@intel.com
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2019-11-18 Matt Roperdrm/i915/vbt: Parse panel options separately from timing...
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
...msgid/20191115165132.9472-2-matthew.d.roper@intel.com
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2019-11-13 Matt Roperdrm/i915/tgl: MOCS table update
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
...msgid/20191112224757.25116-2-matthew.d.roper@intel.com
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2019-11-13 Matt RoperRevert "drm/i915/ehl: Update MOCS table for EHL"
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
...msgid/20191112224757.25116-1-matthew.d.roper@intel.com
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2019-11-07 Matt Roperdrm/i915: Expand documentation for gen12 DP pre-enable...
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
...msgid/20191107174527.11165-1-matthew.d.roper@intel.com
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2019-10-29 Matt Roperdrm/i915: Provide more information on DP AUX failures
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
...msgid/20191029173102.9451-1-matthew.d.roper@intel.com
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2019-10-29 Matt Roperdrm/i915/tgl: Add AUX B & C to DC_OFF_POWER_DOMAINS
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
...msgid/20191025230623.27829-6-matthew.d.roper@intel.com
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2019-10-29 Matt Roperdrm/i915: Drop unused AUX register offsets
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
...msgid/20191026051226.30807-1-matthew.d.roper@intel.com
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2019-10-28 Matt Roperdrm/i915/tgl: Handle AUX interrupts for TC ports
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
...msgid/20191024173023.22113-1-matthew.d.roper@intel.com
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2019-10-24 Matt Roperdrm/i915: Catch GTT fault errors for gen11+ planes
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
...msgid/20191008211716.8391-1-matthew.d.roper@intel.com
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2019-10-22 James Ausmusdrm/i915/aml: Allow SPT PCH for all AML devices
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
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2019-10-18 Vivek Kasireddydrm/i915: Correct the PCH type in irq postinstall
Cc: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
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2019-10-16 Matt Roperdrm/i915: Introduce Jasper Lake PCH
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
...msgid/20191015162854.30546-1-matthew.d.roper@intel.com
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2019-10-16 Matt Roperdrm/i915/ehl: Don't forget to set TC long detect function
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
...msgid/20191015161131.21239-1-matthew.d.roper@intel.com
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2019-10-14 Vivek Kasireddydrm/i915/ehl: Port C's hotplug interrupt is associated...
Suggested-by: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
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2019-10-09 Matt Roperdrm/i915: Select DPLL's via mask
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
...msgid/20191008172920.11362-1-matthew.d.roper@intel.com
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2019-10-07 Matt Roperdrm/i915/vbt: Child device size remains unchanged through...
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
...msgid/20191002192258.1013-1-matthew.d.roper@intel.com
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2019-09-26 Matt Roperdrm/i915: Small joiner RAM buffer size is platform...
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
...msgid/20190925234542.24289-1-matthew.d.roper@intel.com
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2019-09-19 Radhakrishna Sripadadrm/i915/tgl: Implement Wa_1409142259
Cc: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
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2019-09-19 Matt Roperdrm/i915: Unify ICP and MCC hotplug pin tables
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
...msgid/20190918235626.3750-2-matthew.d.roper@intel.com
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2019-09-19 Matt Roperdrm/i915: Future-proof DDC pin mapping
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
...msgid/20190918235626.3750-1-matthew.d.roper@intel.com
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2019-09-11 Matt Roperdrm/i915: Consolidate {bxt,cnl,icl}_init_cdclk
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
...msgid/20190910154252.30503-9-matthew.d.roper@intel.com
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2019-09-11 Matt Roperdrm/i915: Enhance cdclk sanitization
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
...msgid/20190910154252.30503-8-matthew.d.roper@intel.com
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2019-09-11 Matt Roperdrm/i915: Add calc_voltage_level display vfunc
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
...msgid/20190910154252.30503-7-matthew.d.roper@intel.com
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2019-09-11 Matt Roperdrm/i915: Consolidate {bxt,cnl,icl}_uninit_cdclk
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
...msgid/20190910154252.30503-6-matthew.d.roper@intel.com
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2019-09-11 Matt Roperdrm/i915: Kill cnl_sanitize_cdclk()
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
...msgid/20190910154252.30503-5-matthew.d.roper@intel.com
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2019-09-11 Matt Roperdrm/i915: Combine bxt_set_cdclk and cnl_set_cdclk
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
...msgid/20190910154252.30503-4-matthew.d.roper@intel.com
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2019-09-11 Matt Roperdrm/i915: Use literal representation of cdclk tables
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
...msgid/20190910161506.7158-1-matthew.d.roper@intel.com
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2019-09-11 Matt Roperdrm/i915: Consolidate bxt/cnl/icl cdclk readout
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
...msgid/20190910160520.6587-1-matthew.d.roper@intel.com
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2019-09-06 Matt Roperdrm/i915/tgl: Use refclk/2 as bypass frequency
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
...msgid/20190905181337.23727-1-matthew.d.roper@intel.com
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2019-08-30 Matt Roperdrm/i915: Add 324mhz and 326.4mhz cdclks for gen11+
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
...msgid/20190826225540.11987-3-matthew.d.roper@intel.com
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2019-08-30 Matt Roperdrm/i915: Allow /2 CD2X divider on gen11+
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
...msgid/20190830004828.19359-1-matthew.d.roper@intel.com
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2019-08-19 Matt Roperdrm/i915/gen11: Allow usage of all GPIO pins
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
...msgid/20190817005041.20651-1-matthew.d.roper@intel.com
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2019-08-01 Matt Roperdrm/i915/ehl: Don't forget to handle port C's hotplug...
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
...msgid/20190730220553.15300-1-matthew.d.roper@intel.com
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2019-07-15 Matt Roperdrm/i915/ehl: Map MCC pins based on PHY, not port
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
...msgid/20190712221641.21031-1-matthew.d.roper@intel.com
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2019-07-11 Matt Roperdrm/i915/ehl: Enable DDI-D
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
...msgid/20190709183934.445-6-matthew.d.roper@intel.com
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