projects / linux-2.6-microblaze.git / search
| 2020-06-04 | Matt Roper | drm/i915/rkl: Set transcoder mask properly Signed-off-by: Matt Roper <matthew.d.roper@intel.com> |
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| 2020-05-05 | Matt Roper | drm/i915/icp: Add Wa_14010685332 Signed-off-by: Matt Roper <matthew.d.roper@intel.com> |
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| 2020-04-27 | Matt Roper | drm/i915: Use proper fault mask in interrupt postinstall too Signed-off-by: Matt Roper <matthew.d.roper@intel.com> |
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| 2020-04-21 | Matt Roper | drm/i915: Use single set of AUX powerwell ops for gen11+ Signed-off-by: Matt Roper <matthew.d.roper@intel.com> |
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| 2020-04-17 | Matt Roper | drm/i915/tgl: TBT AUX should use TC power well ops Signed-off-by: Matt Roper <matthew.d.roper@intel.com> |
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| 2020-04-15 | Matt Roper | drm/i915/tgl: Initialize multicast register steering... Signed-off-by: Matt Roper <matthew.d.roper@intel.com> |
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| 2020-04-15 | Matt Roper | drm/i915/tgl: Extend Wa_1409767108:tgl to B0 stepping Signed-off-by: Matt Roper <matthew.d.roper@intel.com> |
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| 2020-04-15 | Matt Roper | drm/i915/tgl: Add Wa_14010477008:tgl Signed-off-by: Matt Roper <matthew.d.roper@intel.com> |
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| 2020-04-15 | Matt Atwood | drm/i915/ehl: extended Wa_2006604312 to ehl Signed-off-by: Matt Roper <matthew.d.roper@intel.com> Reviewed-by: Matt Roper <matthew.d.roper@intel.com> |
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| 2020-04-02 | Swathi Dhanavanthri | drm/i915/tgl: Make Wa_14010229206 permanent Reviewed-by: Matt Roper <matthew.d.roper@intel.com> Signed-off-by: Matt Roper <matthew.d.roper@intel.com> |
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| 2020-03-19 | Swathi Dhanavanthri | drm/i915/tgl: Add new PCI IDs to TGL Signed-off-by: Matt Roper <matthew.d.roper@intel.com> Reviewed-by: Matt Roper <matthew.d.roper@intel.com> |
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| 2020-03-13 | Matt Roper | drm/i915: Add Wa_1605460711 / Wa_1408767742 to ICL... Signed-off-by: Matt Roper <matthew.d.roper@intel.com> |
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| 2020-03-13 | Matt Roper | drm/i915: Apply Wa_1406680159:icl,ehl as an engine... Signed-off-by: Matt Roper <matthew.d.roper@intel.com> |
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| 2020-03-13 | Matt Roper | drm/i915: Add Wa_1406306137:icl,ehl Signed-off-by: Matt Roper <matthew.d.roper@intel.com> |
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| 2020-03-13 | Matt Roper | drm/i915: Add Wa_1604278689:icl,ehl Signed-off-by: Matt Roper <matthew.d.roper@intel.com> |
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| 2020-03-13 | Matt Roper | drm/i915: Add Wa_1209644611:icl,ehl Signed-off-by: Matt Roper <matthew.d.roper@intel.com> |
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| 2020-03-13 | Matt Roper | drm/i915: Handle all MCR ranges Signed-off-by: Matt Roper <matthew.d.roper@intel.com> |
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| 2020-03-09 | Matt Roper | drm/i915/tgl: Don't treat unslice registers as masked Signed-off-by: Matt Roper <matthew.d.roper@intel.com> |
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| 2020-03-04 | Matt Roper | drm/i915/ehl: Check PHY type before reading DPLL frequency Signed-off-by: Matt Roper <matthew.d.roper@intel.com> |
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| 2020-02-26 | Matt Atwood | drm/i915/tgl: Add Wa_1606054188:tgl Cc: Matt Roper <matthew.d.roper@intel.com> Signed-off-by: Matt Roper <matthew.d.roper@intel.com> |
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| 2020-02-26 | Matt Roper | drm/i915/tgl: Allow DC5/DC6 entry while PG2 is active Signed-off-by: Matt Roper <matthew.d.roper@intel.com> |
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| 2020-02-21 | Matt Roper | drm/i915/tgl: Add Wa_22010178259:tgl Signed-off-by: Matt Roper <matthew.d.roper@intel.com> |
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| 2020-02-20 | Matt Roper | drm/i915/tgl: Program MBUS_ABOX{1,2}_CTL during display... Signed-off-by: Matt Roper <matthew.d.roper@intel.com> |
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| 2020-02-20 | Matt Roper | drm/i915: Program MBUS with rmw during initialization Signed-off-by: Matt Roper <matthew.d.roper@intel.com> |
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| 2020-02-18 | Rafael Antognolli | drm/i915/tgl: Add Wa_1808121037 to tgl. Signed-off-by: Matt Roper <matthew.d.roper@intel.com> Reviewed-by: Matt Roper <matthew.d.roper@intel.com> |
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| 2020-02-10 | Matt Roper | drm/i915/tgl: Update cdclk voltage level settings Signed-off-by: Matt Roper <matthew.d.roper@intel.com> |
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| 2020-02-10 | Matt Roper | drm/i915/ehl: Update port clock voltage level requirements Signed-off-by: Matt Roper <matthew.d.roper@intel.com> |
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| 2020-01-16 | Matt Atwood | drm/i915: add Wa_14010594013: icl,ehl Signed-off-by: Matt Roper <matthew.d.roper@intel.com> |
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| 2020-01-15 | Radhakrishna Sripada | drm/i915/tgl: Add Wa_1409825376 to tgl Reviewed-by: Matt Roper <matthew.d.roper@intel.com> Signed-off-by: Matt Roper <matthew.d.roper@intel.com> |
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| 2020-01-14 | Matt Roper | drm/i915/gen11: Add additional pcode status values Signed-off-by: Matt Roper <matthew.d.roper@intel.com> |
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| 2020-01-10 | Vivek Kasireddy | drm/i915/dsi: Parse the I2C element from the VBT MIPI... Cc: Matt Roper <matthew.d.roper@intel.com> Signed-off-by: Matt Roper <matthew.d.roper@intel.com> |
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| 2020-01-06 | Kai Vehmanen | drm/i915: Limit audio CDCLK>=2*BCLK constraint back... Reviewed-by: Matt Roper <matthew.d.roper@intel.com> Signed-off-by: Matt Roper <matthew.d.roper@intel.com> |
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| 2020-01-01 | Matt Roper | drm/i915: Add Wa_1407352427:icl,ehl Signed-off-by: Matt Roper <matthew.d.roper@intel.com> |
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| 2019-12-31 | Matt Roper | drm/i915/tgl: Assume future platforms will inherit... Signed-off-by: Matt Roper <matthew.d.roper@intel.com> |
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| 2019-12-27 | Matt Roper | drm/i915/tgl: Extend Wa_1408615072 to tgl Signed-off-by: Matt Roper <matthew.d.roper@intel.com> |
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| 2019-12-27 | Matt Roper | drm/i915: Add Wa_1408615072 and Wa_1407596294 to icl,ehl Signed-off-by: Matt Roper <matthew.d.roper@intel.com> |
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| 2019-12-27 | Matt Roper | drm/i915: Extend WaDisableDARBFClkGating to icl,ehl,tgl Signed-off-by: Matt Roper <matthew.d.roper@intel.com> |
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| 2019-12-13 | Matt Roper | drm/i915/icl: Cleanup combo PHY aux power well handlers Signed-off-by: Matt Roper <matthew.d.roper@intel.com> |
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| 2019-12-13 | Matt Roper | drm/i915/tgl: Drop Wa#1178 Signed-off-by: Matt Roper <matthew.d.roper@intel.com> |
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| 2019-12-13 | Matt Roper | drm/i915/ehl: Define EHL powerwells independently of ICL Signed-off-by: Matt Roper <matthew.d.roper@intel.com> |
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| 2019-12-10 | Matt Roper | drm/i915/tgl: Program BW_BUDDY registers during display... Signed-off-by: Matt Roper <matthew.d.roper@intel.com> |
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| 2019-12-03 | Matt Roper | drm/i915/irq: Refactor gen11 display interrupt handling Signed-off-by: Matt Roper <matthew.d.roper@intel.com> |
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| 2019-12-02 | Matt Roper | drm/i915: Program SHPD_FILTER_CNT on CNP+ Signed-off-by: Matt Roper <matthew.d.roper@intel.com> |
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| 2019-12-02 | Matt Roper | drm/i915/ehl: Make icp_digital_port_connected() use... Signed-off-by: Matt Roper <matthew.d.roper@intel.com> |
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| 2019-12-02 | Matt Roper | drm/i915: Handle SDEISR according to PCH rather than... Signed-off-by: Matt Roper <matthew.d.roper@intel.com> |
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| 2019-11-27 | Kai Vehmanen | drm/i915/dp: fix DP audio for PORT_A on gen12+ Reviewed-by: Matt Roper <matthew.d.roper@intel.com> Signed-off-by: Matt Roper <matthew.d.roper@intel.com> |
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| 2019-11-19 | Matt Roper | drm/i915/tgl: Add DKL PHY vswing table for HDMI Signed-off-by: Matt Roper <matthew.d.roper@intel.com> |
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| 2019-11-19 | Matt Roper | drm/i915/ehl: Update voltage level checks Signed-off-by: Matt Roper <matthew.d.roper@intel.com> |
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| 2019-11-18 | Matt Roper | drm/i915/vbt: Handle generic DTD block Signed-off-by: Matt Roper <matthew.d.roper@intel.com> |
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| 2019-11-18 | Matt Roper | drm/i915/vbt: Parse panel options separately from timing... Signed-off-by: Matt Roper <matthew.d.roper@intel.com> |
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| 2019-11-13 | Matt Roper | drm/i915/tgl: MOCS table update Signed-off-by: Matt Roper <matthew.d.roper@intel.com> |
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| 2019-11-13 | Matt Roper | Revert "drm/i915/ehl: Update MOCS table for EHL" Signed-off-by: Matt Roper <matthew.d.roper@intel.com> |
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| 2019-11-07 | Matt Roper | drm/i915: Expand documentation for gen12 DP pre-enable... Signed-off-by: Matt Roper <matthew.d.roper@intel.com> |
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| 2019-10-29 | Matt Roper | drm/i915: Provide more information on DP AUX failures Signed-off-by: Matt Roper <matthew.d.roper@intel.com> |
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| 2019-10-29 | Matt Roper | drm/i915/tgl: Add AUX B & C to DC_OFF_POWER_DOMAINS Signed-off-by: Matt Roper <matthew.d.roper@intel.com> |
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| 2019-10-29 | Matt Roper | drm/i915: Drop unused AUX register offsets Signed-off-by: Matt Roper <matthew.d.roper@intel.com> |
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| 2019-10-28 | Matt Roper | drm/i915/tgl: Handle AUX interrupts for TC ports Signed-off-by: Matt Roper <matthew.d.roper@intel.com> |
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| 2019-10-24 | Matt Roper | drm/i915: Catch GTT fault errors for gen11+ planes Signed-off-by: Matt Roper <matthew.d.roper@intel.com> |
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| 2019-10-22 | James Ausmus | drm/i915/aml: Allow SPT PCH for all AML devices Signed-off-by: Matt Roper <matthew.d.roper@intel.com> |
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| 2019-10-18 | Vivek Kasireddy | drm/i915: Correct the PCH type in irq postinstall Cc: Matt Roper <matthew.d.roper@intel.com> Reviewed-by: Matt Roper <matthew.d.roper@intel.com> Signed-off-by: Matt Roper <matthew.d.roper@intel.com> |
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| 2019-10-16 | Matt Roper | drm/i915: Introduce Jasper Lake PCH Signed-off-by: Matt Roper <matthew.d.roper@intel.com> |
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| 2019-10-16 | Matt Roper | drm/i915/ehl: Don't forget to set TC long detect function Signed-off-by: Matt Roper <matthew.d.roper@intel.com> |
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| 2019-10-14 | Vivek Kasireddy | drm/i915/ehl: Port C's hotplug interrupt is associated... Suggested-by: Matt Roper <matthew.d.roper@intel.com> Reviewed-by: Matt Roper <matthew.d.roper@intel.com> Signed-off-by: Matt Roper <matthew.d.roper@intel.com> |
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| 2019-10-09 | Matt Roper | drm/i915: Select DPLL's via mask Signed-off-by: Matt Roper <matthew.d.roper@intel.com> |
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| 2019-10-07 | Matt Roper | drm/i915/vbt: Child device size remains unchanged through... Signed-off-by: Matt Roper <matthew.d.roper@intel.com> |
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| 2019-09-26 | Matt Roper | drm/i915: Small joiner RAM buffer size is platform... Signed-off-by: Matt Roper <matthew.d.roper@intel.com> |
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| 2019-09-19 | Radhakrishna Sripada | drm/i915/tgl: Implement Wa_1409142259 Cc: Matt Roper <matthew.d.roper@intel.com> Signed-off-by: Matt Roper <matthew.d.roper@intel.com> |
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| 2019-09-19 | Matt Roper | drm/i915: Unify ICP and MCC hotplug pin tables Signed-off-by: Matt Roper <matthew.d.roper@intel.com> |
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| 2019-09-19 | Matt Roper | drm/i915: Future-proof DDC pin mapping Signed-off-by: Matt Roper <matthew.d.roper@intel.com> |
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| 2019-09-11 | Matt Roper | drm/i915: Consolidate {bxt,cnl,icl}_init_cdclk Signed-off-by: Matt Roper <matthew.d.roper@intel.com> |
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| 2019-09-11 | Matt Roper | drm/i915: Enhance cdclk sanitization Signed-off-by: Matt Roper <matthew.d.roper@intel.com> |
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| 2019-09-11 | Matt Roper | drm/i915: Add calc_voltage_level display vfunc Signed-off-by: Matt Roper <matthew.d.roper@intel.com> |
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| 2019-09-11 | Matt Roper | drm/i915: Consolidate {bxt,cnl,icl}_uninit_cdclk Signed-off-by: Matt Roper <matthew.d.roper@intel.com> |
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| 2019-09-11 | Matt Roper | drm/i915: Kill cnl_sanitize_cdclk() Signed-off-by: Matt Roper <matthew.d.roper@intel.com> |
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| 2019-09-11 | Matt Roper | drm/i915: Combine bxt_set_cdclk and cnl_set_cdclk Signed-off-by: Matt Roper <matthew.d.roper@intel.com> |
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| 2019-09-11 | Matt Roper | drm/i915: Use literal representation of cdclk tables Signed-off-by: Matt Roper <matthew.d.roper@intel.com> |
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| 2019-09-11 | Matt Roper | drm/i915: Consolidate bxt/cnl/icl cdclk readout Signed-off-by: Matt Roper <matthew.d.roper@intel.com> |
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| 2019-09-06 | Matt Roper | drm/i915/tgl: Use refclk/2 as bypass frequency Signed-off-by: Matt Roper <matthew.d.roper@intel.com> |
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| 2019-08-30 | Matt Roper | drm/i915: Add 324mhz and 326.4mhz cdclks for gen11+ Signed-off-by: Matt Roper <matthew.d.roper@intel.com> |
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| 2019-08-30 | Matt Roper | drm/i915: Allow /2 CD2X divider on gen11+ Signed-off-by: Matt Roper <matthew.d.roper@intel.com> |
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| 2019-08-19 | Matt Roper | drm/i915/gen11: Allow usage of all GPIO pins Signed-off-by: Matt Roper <matthew.d.roper@intel.com> |
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| 2019-08-01 | Matt Roper | drm/i915/ehl: Don't forget to handle port C's hotplug... Signed-off-by: Matt Roper <matthew.d.roper@intel.com> |
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| 2019-07-15 | Matt Roper | drm/i915/ehl: Map MCC pins based on PHY, not port Signed-off-by: Matt Roper <matthew.d.roper@intel.com> |
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| 2019-07-11 | Matt Roper | drm/i915/ehl: Enable DDI-D Signed-off-by: Matt Roper <matthew.d.roper@intel.com> |
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| 2019-07-11 | Matt Roper | drm/i915: Transition port type checks to phy checks Signed-off-by: Matt Roper <matthew.d.roper@intel.com> |
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| 2019-07-11 | Matt Roper | drm/i915/gen11: Convert combo PHY logic to use new... Signed-off-by: Matt Roper <matthew.d.roper@intel.com> |
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| 2019-07-11 | Matt Roper | drm/i915/gen11: Program ICL_DPCLKA_CFGCR0 according... Signed-off-by: Matt Roper <matthew.d.roper@intel.com> |
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| 2019-07-11 | Matt Roper | drm/i915/gen11: Start distinguishing 'phy' from 'port' Signed-off-by: Matt Roper <matthew.d.roper@intel.com> |
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| 2019-07-01 | Matt Roper | drm/i915/ehl: Don't program PHY_MISC on EHL PHY C Signed-off-by: Matt Roper <matthew.d.roper@intel.com> |
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| 2019-07-01 | Matt Roper | drm/i915/ehl: Add third combo PHY offset Signed-off-by: Matt Roper <matthew.d.roper@intel.com> |
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| 2019-07-01 | Matt Roper | drm/i915/icl: Drop port parameter to icl_get_combo_buf_trans() Signed-off-by: Matt Roper <matthew.d.roper@intel.com> |
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| 2019-06-25 | Matt Roper | drm/i915/ehl: Add one additional PCH ID to MCC Signed-off-by: Matt Roper <matthew.d.roper@intel.com> |
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| 2019-06-19 | Matt Roper | drm/i915/ehl: Allow combo PHY A to drive a third external... Signed-off-by: Matt Roper <matthew.d.roper@intel.com> |
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| 2019-06-17 | Matt Roper | drm/i915/ehl: Introduce Mule Creek Canyon PCH Signed-off-by: Matt Roper <matthew.d.roper@intel.com> |
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| 2019-06-15 | Matt Roper | drm/i915/ehl: Update MOCS table for EHL Signed-off-by: Matt Roper <matthew.d.roper@intel.com> |
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| 2019-06-14 | Matt Roper | drm/i915: Add Wa_1409120013:icl,ehl Signed-off-by: Matt Roper <matthew.d.roper@intel.com> |
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| 2019-06-05 | Matt Roper | drm/i915/ehl: Support HBR3 on EHL combo PHY Signed-off-by: Matt Roper <matthew.d.roper@intel.com> |
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| 2019-01-31 | Matt Roper | drm/i915: Apply LUT validation checks to platforms... Signed-off-by: Matt Roper <matthew.d.roper@intel.com> |
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| 2019-01-31 | Matt Roper | drm/i915: Force background color to black for gen9... Signed-off-by: Matt Roper <matthew.d.roper@intel.com> |
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| 2019-01-24 | Matt Roper | drm/i915: Validate userspace-provided color management... Signed-off-by: Matt Roper <matthew.d.roper@intel.com> |
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