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2020-03-05	Tycho Andersen	riscv: fix seccomp reject syscall code path Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com>	commit \| commitdiff \| tree
2020-03-05	Yash Shah	riscv: dts: Add GPIO reboot method to HiFive Unleashed... Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com>	commit \| commitdiff \| tree
2020-03-05	Anup Patel	RISC-V: Select Goldfish RTC driver for QEMU virt machine Reviewed-by: Palmer Dabbelt <palmerdabbelt@google.com> Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com>	commit \| commitdiff \| tree
2020-03-05	Anup Patel	RISC-V: Select SYSCON Reboot and Poweroff for QEMU... Reviewed-by: Palmer Dabbelt <palmerdabbelt@google.com> Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com>	commit \| commitdiff \| tree
2020-03-05	Anup Patel	RISC-V: Enable QEMU virt machine support in defconfigs Reviewed-by: Palmer Dabbelt <palmerdabbelt@google.com> Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com>	commit \| commitdiff \| tree
2020-03-05	Anup Patel	RISC-V: Add kconfig option for QEMU virt machine Reviewed-by: Palmer Dabbelt <palmerdabbelt@google.com> Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com>	commit \| commitdiff \| tree
2020-03-04	Alexandre Ghiti	riscv: Fix range looking for kernel image memblock Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com>	commit \| commitdiff \| tree
2020-03-04	Damien Le Moal	riscv: Force flat memory model with no-mmu Reviewed-by: Palmer Dabbelt <palmerdabbelt@google.com> Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com>	commit \| commitdiff \| tree
2020-03-03	Vincent Chen	riscv: Change code model of module to medany to improve... Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com>	commit \| commitdiff \| tree
2020-03-03	Vincent Chen	riscv: avoid the PIC offset of static percpu data in... Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com>	commit \| commitdiff \| tree
2020-02-24	Zong Li	riscv: adjust the indent Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com>	commit \| commitdiff \| tree
2020-02-24	Zong Li	riscv: allocate a complete page size for each page... Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com>	commit \| commitdiff \| tree
2020-02-20	Damien Le Moal	riscv: Fix gitignore Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com>	commit \| commitdiff \| tree
2020-02-18	Anup Patel	RISC-V: Don't enable all interrupts in trap_init() Tested-by: Palmer Dabbelt <palmerdabbelt@google.com> [QMEU... Reviewed-by: Palmer Dabbelt <palmerdabbelt@google.com> Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com>	commit \| commitdiff \| tree
2020-02-18	Greentime Hu	riscv: set pmp configuration if kernel is running in... Reviewed-by: Palmer Dabbelt <palmerdabbelt@google.com> Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com>	commit \| commitdiff \| tree
2020-01-29	Yash Shah	riscv: dts: Add DT support for SiFive FU540 GPIO driver Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com>	commit \| commitdiff \| tree
2020-01-23	Zong Li	riscv: mm: add support for CONFIG_DEBUG_VIRTUAL Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com>	commit \| commitdiff \| tree
2020-01-22	Olof Johansson	riscv: keep 32-bit kernel to 32-bit phys_addr_t Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com>	commit \| commitdiff \| tree
2020-01-22	Nick Hu	kasan: Add riscv to KASAN documentation. Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com>	commit \| commitdiff \| tree
2020-01-22	Nick Hu	riscv: Add KASAN support Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com>	commit \| commitdiff \| tree
2020-01-22	Nick Hu	kasan: No KASAN's memmove check if archs don't have it. Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com>	commit \| commitdiff \| tree
2019-05-17	Andreas Schwab	riscv: fix locking violation in page fault handler Signed-off-by: Palmer Dabbelt <palmer@sifive.com>	commit \| commitdiff \| tree
2019-05-17	Yash Shah	RISC-V: sifive_l2_cache: Add L2 cache controller driver... Signed-off-by: Palmer Dabbelt <palmer@sifive.com>	commit \| commitdiff \| tree
2019-05-17	Yash Shah	RISC-V: Add DT documentation for SiFive L2 Cache Controller Signed-off-by: Palmer Dabbelt <palmer@sifive.com>	commit \| commitdiff \| tree
2019-05-17	Palmer Dabbelt	RISC-V: Avoid using invalid intermediate translations Signed-off-by: Palmer Dabbelt <palmer@sifive.com>	commit \| commitdiff \| tree
2019-05-17	Vincent Chen	riscv: Support BUG() in kernel module Signed-off-by: Palmer Dabbelt <palmer@sifive.com>	commit \| commitdiff \| tree
2019-05-17	Vincent Chen	riscv: Add the support for c.ebreak check in is_valid_bugaddr() Signed-off-by: Palmer Dabbelt <palmer@sifive.com>	commit \| commitdiff \| tree
2019-05-17	Vincent Chen	riscv: support trap-based WARN() Signed-off-by: Palmer Dabbelt <palmer@sifive.com>	commit \| commitdiff \| tree
2019-05-17	Gary Guo	riscv: fix sbi_remote_sfence_vma{,_asid}. Signed-off-by: Palmer Dabbelt <palmer@sifive.com>	commit \| commitdiff \| tree
2019-05-17	Gary Guo	riscv: move switch_mm to its own file Signed-off-by: Palmer Dabbelt <palmer@sifive.com>	commit \| commitdiff \| tree
2019-05-17	Gary Guo	riscv: move flush_icache_{all,mm} to cacheflush.c Signed-off-by: Palmer Dabbelt <palmer@sifive.com>	commit \| commitdiff \| tree
2019-05-17	Anup Patel	tty: Don't force RISCV SBI console as preferred console Signed-off-by: Palmer Dabbelt <palmer@sifive.com>	commit \| commitdiff \| tree
2019-05-17	Anup Patel	RISC-V: Access CSRs using CSR numbers Signed-off-by: Palmer Dabbelt <palmer@sifive.com>	commit \| commitdiff \| tree
2019-05-17	Anup Patel	RISC-V: Add interrupt related SCAUSE defines in asm... Signed-off-by: Palmer Dabbelt <palmer@sifive.com>	commit \| commitdiff \| tree
2019-05-17	Anup Patel	RISC-V: Use tabs to align macro values in asm/csr.h Signed-off-by: Palmer Dabbelt <palmer@sifive.com>	commit \| commitdiff \| tree
2019-05-17	Atish Patra	RISC-V: Fix minor checkpatch issues. Signed-off-by: Palmer Dabbelt <palmer@sifive.com>	commit \| commitdiff \| tree
2019-05-17	Atish Patra	RISC-V: Support nr_cpus command line option. Signed-off-by: Palmer Dabbelt <palmer@sifive.com>	commit \| commitdiff \| tree
2019-04-30	Atish Patra	RISC-V: Implement nosmp commandline option. Signed-off-by: Palmer Dabbelt <palmer@sifive.com>	commit \| commitdiff \| tree
2019-04-30	Atish Patra	RISC-V: Add RISC-V specific arch_match_cpu_phys_id Signed-off-by: Palmer Dabbelt <palmer@sifive.com>	commit \| commitdiff \| tree
2019-04-29	Nick Desaulniers	riscv: vdso: drop unnecessary cc-ldoption Signed-off-by: Palmer Dabbelt <palmer@sifive.com>	commit \| commitdiff \| tree
2019-04-25	Christoph Hellwig	riscv: call pm_power_off from machine_halt / machine_power_off Signed-off-by: Palmer Dabbelt <palmer@sifive.com>	commit \| commitdiff \| tree
2019-04-25	Christoph Hellwig	riscv: print the unexpected interrupt cause Signed-off-by: Palmer Dabbelt <palmer@sifive.com>	commit \| commitdiff \| tree
2019-04-25	Christoph Hellwig	riscv: remove duplicate macros from ptrace.h Signed-off-by: Palmer Dabbelt <palmer@sifive.com>	commit \| commitdiff \| tree
2019-04-25	Christoph Hellwig	riscv: remove unreachable !HAVE_FUNCTION_GRAPH_RET_ADDR_PTR... Signed-off-by: Palmer Dabbelt <palmer@sifive.com>	commit \| commitdiff \| tree
2019-04-25	Christoph Hellwig	riscv: cleanup the parse_dtb calling conventions Signed-off-by: Palmer Dabbelt <palmer@sifive.com>	commit \| commitdiff \| tree
2019-04-25	Christoph Hellwig	riscv: simplify the stack pointer setup in head.S Signed-off-by: Palmer Dabbelt <palmer@sifive.com>	commit \| commitdiff \| tree
2019-04-25	Christoph Hellwig	riscv: clear all pending interrupts when booting Signed-off-by: Palmer Dabbelt <palmer@sifive.com>	commit \| commitdiff \| tree
2019-04-25	Christoph Hellwig	riscv: remove CONFIG_RISCV_ISA_A Signed-off-by: Palmer Dabbelt <palmer@sifive.com>	commit \| commitdiff \| tree
2019-04-25	Christoph Hellwig	riscv: remove unreachable big endian code Signed-off-by: Palmer Dabbelt <palmer@sifive.com>	commit \| commitdiff \| tree
2019-04-25	Christoph Hellwig	riscv: turn mm_segment_t into a struct Signed-off-by: Palmer Dabbelt <palmer@sifive.com>	commit \| commitdiff \| tree
2019-04-25	Christoph Hellwig	riscv: use asm-generic/extable.h Signed-off-by: Palmer Dabbelt <palmer@sifive.com>	commit \| commitdiff \| tree
2019-04-25	Guo Ren	riscv/signal: Fixup additional syscall restarting Signed-off-by: Palmer Dabbelt <palmer@sifive.com>	commit \| commitdiff \| tree
2019-04-10	Anup Patel	RISC-V: Fix Maximum Physical Memory 2GiB option for... Signed-off-by: Palmer Dabbelt <palmer@sifive.com>	commit \| commitdiff \| tree
2019-04-10	Paul Walmsley	dt-bindings: clock: sifive: add FU540-C000 PRCI clock... Signed-off-by: Palmer Dabbelt <palmer@sifive.com>	commit \| commitdiff \| tree
2019-04-09	Anup Patel	RISC-V: Add separate defconfig for 32bit systems Signed-off-by: Palmer Dabbelt <palmer@sifive.com>	commit \| commitdiff \| tree
2019-03-29	Joe Perches	RISC-V: Use IS_ENABLED(CONFIG_CMODEL_MEDLOW) Signed-off-by: Palmer Dabbelt <palmer@sifive.com>	commit \| commitdiff \| tree
2019-03-29	Anup Patel	RISC-V: Fix FIXMAP_TOP to avoid overlap with VMALLOC... Signed-off-by: Palmer Dabbelt <palmer@sifive.com>	commit \| commitdiff \| tree
2019-03-27	Anup Patel	RISC-V: Always compile mm/init.c with cmodel=medany... Signed-off-by: Palmer Dabbelt <palmer@sifive.com>	commit \| commitdiff \| tree
2019-03-27	Alan Kao	riscv: fix accessing 8-byte variable from RV32 Signed-off-by: Palmer Dabbelt <palmer@sifive.com>	commit \| commitdiff \| tree
2019-03-04	Palmer Dabbelt	RISC-V: Fixmap support and MM cleanups	commit \| commitdiff \| tree
2019-03-04	Andreas Schwab	arch: riscv: fix logic error in parse_dtb Signed-off-by: Palmer Dabbelt <palmer@sifive.com>	commit \| commitdiff \| tree
2019-03-04	Atish Patra	RISC-V: Assign hwcap as per comman capabilities. Signed-off-by: Palmer Dabbelt <palmer@sifive.com>	commit \| commitdiff \| tree
2019-03-04	Atish Patra	RISC-V: Compare cpuid with NR_CPUS before mapping. Signed-off-by: Palmer Dabbelt <palmer@sifive.com>	commit \| commitdiff \| tree
2019-03-04	Atish Patra	RISC-V: Allow hartid-to-cpuid function to fail. Signed-off-by: Palmer Dabbelt <palmer@sifive.com>	commit \| commitdiff \| tree
2019-03-04	Atish Patra	RISC-V: Remove NR_CPUs check during hartid search from DT Signed-off-by: Palmer Dabbelt <palmer@sifive.com>	commit \| commitdiff \| tree
2019-03-04	Atish Patra	RISC-V: Move cpuid to hartid mapping to SMP. Signed-off-by: Palmer Dabbelt <palmer@sifive.com>	commit \| commitdiff \| tree
2019-03-04	Atish Patra	RISC-V: Do not wait indefinitely in __cpu_up Signed-off-by: Palmer Dabbelt <palmer@sifive.com>	commit \| commitdiff \| tree
2019-02-19	Christoph Hellwig	riscv: remove the HAVE_KPROBES option Signed-off-by: Palmer Dabbelt <palmer@sifive.com>	commit \| commitdiff \| tree
2019-02-11	Johan Hovold	riscv: use for_each_of_cpu_node iterator Signed-off-by: Palmer Dabbelt <palmer@sifive.com>	commit \| commitdiff \| tree
2019-02-11	Johan Hovold	riscv: treat cpu devicetree nodes without status as... Signed-off-by: Palmer Dabbelt <palmer@sifive.com>	commit \| commitdiff \| tree
2019-02-11	Johan Hovold	riscv: fix riscv_of_processor_hartid() comment Signed-off-by: Palmer Dabbelt <palmer@sifive.com>	commit \| commitdiff \| tree
2019-02-11	Johan Hovold	riscv: use pr_info and friends Signed-off-by: Palmer Dabbelt <palmer@sifive.com>	commit \| commitdiff \| tree
2019-02-11	Johan Hovold	riscv: add missing newlines to printk messages Signed-off-by: Palmer Dabbelt <palmer@sifive.com>	commit \| commitdiff \| tree
2019-02-11	Palmer Dabbelt	Revert "RISC-V: Make BSS section as the last section... Signed-off-by: Palmer Dabbelt <palmer@sifive.com>	commit \| commitdiff \| tree
2019-02-11	Stefan O'Rear	riscv: Add pte bit to distinguish swap from invalid Signed-off-by: Palmer Dabbelt <palmer@sifive.com>	commit \| commitdiff \| tree
2019-01-25	Alexandre Ghiti	riscv: Adjust mmap base address at a third of task... Signed-off-by: Palmer Dabbelt <palmer@sifive.com>	commit \| commitdiff \| tree
2019-01-24	Guo Ren	riscv: fixup max_low_pfn with PFN_DOWN. Signed-off-by: Palmer Dabbelt <palmer@sifive.com>	commit \| commitdiff \| tree
2019-01-23	Andreas Schwab	tty/serial: use uart_console_write in the RISC-V SBL... Signed-off-by: Palmer Dabbelt <palmer@sifive.com>	commit \| commitdiff \| tree
2019-01-23	Palmer Dabbelt	RISC-V: defconfig: Add CRYPTO_DEV_VIRTIO=y Signed-off-by: Palmer Dabbelt <palmer@sifive.com>	commit \| commitdiff \| tree
2019-01-23	Alistair Francis	RISC-V: defconfig: Enable Generic PCIE by default Signed-off-by: Palmer Dabbelt <palmer@sifive.com>	commit \| commitdiff \| tree
2019-01-23	Palmer Dabbelt	RISC-V: defconfig: Move CONFIG_PCI{,E_XILINX} Signed-off-by: Palmer Dabbelt <palmer@sifive.com>	commit \| commitdiff \| tree
2019-01-23	Antony Pavlov	RISC-V: Kconfig: fix spelling mistake "traget" -> ... Signed-off-by: Palmer Dabbelt <palmer@sifive.com>	commit \| commitdiff \| tree
2019-01-23	Antony Pavlov	RISC-V: asm/page.h: fix spelling mistake "CONFIG_64BITS... Signed-off-by: Palmer Dabbelt <palmer@sifive.com>	commit \| commitdiff \| tree
2019-01-23	Andreas Schwab	RISC-V: fix bad use of of_node_put Signed-off-by: Palmer Dabbelt <palmer@sifive.com>	commit \| commitdiff \| tree
2019-01-23	Vincent Chen	RISC-V: Add _TIF_NEED_RESCHED check for kernel thread... Signed-off-by: Palmer Dabbelt <palmer@sifive.com>	commit \| commitdiff \| tree
2019-01-09	Anup Patel	tty/serial: Add RISC-V SBI earlycon support Reviewed-by: Palmer Dabbelt <palmer@sifive.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com>	commit \| commitdiff \| tree
2019-01-07	Palmer Dabbelt	Fix a handful of audit-related issue	commit \| commitdiff \| tree
2019-01-07	David Abdurachmanov	riscv: add HAVE_SYSCALL_TRACEPOINTS to Kconfig Signed-off-by: Palmer Dabbelt <palmer@sifive.com>	commit \| commitdiff \| tree
2019-01-07	David Abdurachmanov	riscv: fix trace_sys_exit hook Signed-off-by: Palmer Dabbelt <palmer@sifive.com>	commit \| commitdiff \| tree
2019-01-07	David Abdurachmanov	riscv: define CREATE_TRACE_POINTS in ptrace.c Signed-off-by: Palmer Dabbelt <palmer@sifive.com>	commit \| commitdiff \| tree
2019-01-07	David Abdurachmanov	riscv: define NR_syscalls in unistd.h Signed-off-by: Palmer Dabbelt <palmer@sifive.com>	commit \| commitdiff \| tree
2019-01-07	David Abdurachmanov	riscv: audit: add audit hook in do_syscall_trace_enter... Signed-off-by: Palmer Dabbelt <palmer@sifive.com>	commit \| commitdiff \| tree
2019-01-07	David Abdurachmanov	riscv: add audit support Signed-off-by: Palmer Dabbelt <palmer@sifive.com>	commit \| commitdiff \| tree
2019-01-07	Zong Li	RISC-V: Support MODULE_SECTIONS mechanism on RV32 Signed-off-by: Palmer Dabbelt <palmer@sifive.com>	commit \| commitdiff \| tree
2019-01-07	Paul Walmsley	MAINTAINERS: SiFive drivers: add myself as a SiFive... Cc: Palmer Dabbelt <palmer@sifive.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com>	commit \| commitdiff \| tree
2019-01-07	Paul Walmsley	MAINTAINERS: SiFive drivers: change the git tree to... Cc: Palmer Dabbelt <palmer@sifive.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com>	commit \| commitdiff \| tree
2019-01-07	Andreas Schwab	riscv: don't stop itself in smp_send_stop Signed-off-by: Palmer Dabbelt <palmer@sifive.com>	commit \| commitdiff \| tree
2019-01-07	Paul Walmsley	arch: riscv: support kernel command line forcing when... Cc: Palmer Dabbelt <palmer@sifive.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com>	commit \| commitdiff \| tree
2019-01-07	Aurelien Jarno	tools uapi: fix RISC-V 64-bit support Signed-off-by: Palmer Dabbelt <palmer@sifive.com>	commit \| commitdiff \| tree
2019-01-07	Anup Patel	RISC-V: Make BSS section as the last section in vmlinux... Signed-off-by: Palmer Dabbelt <palmer@sifive.com>	commit \| commitdiff \| tree
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