projects / linux-2.6-microblaze.git / search
| 2020-04-21 | Guenter Roeck | RISC-V: stacktrace: Declare sp_in_global outside ifdef Reviewed-by: Palmer Dabbelt <palmerdabbelt@google.com> Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com> |
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| 2020-04-03 | Christoph Hellwig | riscv: create a loader.bin boot image for Kendryte SoC Reviewed-by: Palmer Dabbelt <palmerdabbelt@google.com> Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com> |
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| 2020-04-03 | Damien Le Moal | riscv: Kendryte K210 default config Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com> |
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| 2020-04-03 | Damien Le Moal | riscv: Add Kendryte K210 device tree Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com> |
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| 2020-04-03 | Damien Le Moal | riscv: Select required drivers for Kendryte SOC Reviewed-by: Palmer Dabbelt <palmerdabbelt@google.com> Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com> |
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| 2020-04-03 | Christoph Hellwig | riscv: Add Kendryte K210 SoC support Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com> |
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| 2020-04-03 | Damien Le Moal | riscv: Add SOC early init support Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com> |
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| 2020-04-03 | Damien Le Moal | riscv: Unaligned load/store handling for M_MODE Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com> |
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| 2020-03-31 | Atish Patra | RISC-V: Support cpu hotplug |
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| 2020-03-31 | Atish Patra | RISC-V: Add supported for ordered booting method using HSM Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com> |
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| 2020-03-31 | Atish Patra | RISC-V: Add SBI HSM extension definitions Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com> |
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| 2020-03-31 | Atish Patra | RISC-V: Export SBI error to linux error mapping function Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com> |
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| 2020-03-31 | Atish Patra | RISC-V: Add cpu_ops and modify default booting method Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com> |
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| 2020-03-31 | Atish Patra | RISC-V: Move relocate and few other functions out of... Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com> |
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| 2020-03-31 | Atish Patra | RISC-V: Implement new SBI v0.2 extensions Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com> |
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| 2020-03-31 | Atish Patra | RISC-V: Introduce a new config for SBI v0.1 Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com> |
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| 2020-03-31 | Atish Patra | RISC-V: Add SBI v0.2 extension definitions Reviewed-by: Palmer Dabbelt <palmerdabbelt@google.com> Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com> |
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| 2020-03-31 | Atish Patra | RISC-V: Add basic support for SBI v0.2 Reviewed-by: Palmer Dabbelt <palmerdabbelt@google.com> Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com> |
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| 2020-03-31 | Atish Patra | RISC-V: Mark existing SBI as 0.1 SBI. Reviewed-by: Palmer Dabbelt <palmerdabbelt@google.com> Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com> |
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| 2020-03-27 | Atish Patra | RISC-V: Move all address space definition macros to... Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com> |
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| 2020-03-26 | Anup Patel | RISC-V: Only select essential drivers for SOC_VIRT... Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com> |
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| 2020-03-26 | Zong Li | riscv: Use macro definition instead of magic number Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com> |
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| 2020-03-26 | Zong Li | riscv: Add support to dump the kernel page tables Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com> |
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| 2020-03-26 | Zong Li | riscv: patch code by fixmap mapping Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com> |
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| 2020-03-26 | Zong Li | riscv: introduce interfaces to patch kernel code Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com> |
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| 2020-03-26 | Zong Li | riscv: add macro to get instruction length Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com> |
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| 2020-03-26 | Zong Li | riscv: add STRICT_KERNEL_RWX support Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com> |
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| 2020-03-26 | Zong Li | riscv: add alignment for text, rodata and data sections Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com> |
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| 2020-03-26 | Zong Li | riscv: move exception table immediately after RO_DATA Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com> |
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| 2020-03-26 | Zong Li | riscv: add ARCH_SUPPORTS_DEBUG_PAGEALLOC support Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com> |
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| 2020-03-26 | Zong Li | riscv: add ARCH_HAS_SET_DIRECT_MAP support Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com> |
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| 2020-03-26 | Zong Li | riscv: add ARCH_HAS_SET_MEMORY support Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com> |
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| 2020-03-19 | Greentime Hu | riscv: fix the IPI missing issue in nommu mode Reviewed-by: Palmer Dabbelt <palmerdabbelt@google.com> Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com> |
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| 2020-03-19 | Greentime Hu | riscv: uaccess should be used in nommu mode Reviewed-by: Palmer Dabbelt <palmerdabbelt@google.com> Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com> |
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| 2020-03-06 | Atish Patra | RISC-V: Move all address space definition macros to... Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com> |
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| 2020-03-05 | Tycho Andersen | riscv: fix seccomp reject syscall code path Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com> |
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| 2020-03-05 | Alexandre Ghiti | riscv: Use p*d_leaf macros to define p*d_huge Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com> |
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| 2020-03-05 | Yash Shah | riscv: dts: Add GPIO reboot method to HiFive Unleashed... Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com> |
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| 2020-03-05 | Anup Patel | RISC-V: Select Goldfish RTC driver for QEMU virt machine Reviewed-by: Palmer Dabbelt <palmerdabbelt@google.com> Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com> |
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| 2020-03-05 | Anup Patel | RISC-V: Select SYSCON Reboot and Poweroff for QEMU... Reviewed-by: Palmer Dabbelt <palmerdabbelt@google.com> Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com> |
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| 2020-03-05 | Anup Patel | RISC-V: Enable QEMU virt machine support in defconfigs Reviewed-by: Palmer Dabbelt <palmerdabbelt@google.com> Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com> |
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| 2020-03-05 | Anup Patel | RISC-V: Add kconfig option for QEMU virt machine Reviewed-by: Palmer Dabbelt <palmerdabbelt@google.com> Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com> |
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| 2020-03-04 | Alexandre Ghiti | riscv: Fix range looking for kernel image memblock Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com> |
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| 2020-03-04 | Damien Le Moal | riscv: Force flat memory model with no-mmu Reviewed-by: Palmer Dabbelt <palmerdabbelt@google.com> Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com> |
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| 2020-03-03 | Palmer Dabbelt | RISC-V: Stop using LOCAL for the uaccess fixups Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com> |
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| 2020-03-03 | Palmer Dabbelt | RISC-V: Inline the assembly register save/restore macros Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com> |
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| 2020-03-03 | Palmer Dabbelt | RISC-V: Stop relying on GCC's register allocator's... Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com> |
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| 2020-03-03 | Palmer Dabbelt | RISC-V: Stop putting .sbss in .sdata Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com> |
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| 2020-03-03 | Zong Li | riscv: force hart_lottery to put in .sdata section Reviewed-by: Palmer Dabbelt <palmerdabbelt@google.com> Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com> |
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| 2020-03-03 | Deepa Dinamani | riscv: Delete CONFIG_SYSFS_SYSCALL from defconfigs Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com> |
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| 2020-03-03 | Guo Ren | riscv: Use flush_icache_mm for flush_icache_user_range Reviewed-by: Palmer Dabbelt <palmerdabbelt@google.com> Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com> |
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| 2020-03-03 | Vincent Chen | riscv: Change code model of module to medany to improve... Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com> |
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| 2020-03-03 | Vincent Chen | riscv: avoid the PIC offset of static percpu data in... Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com> |
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| 2020-02-24 | Zong Li | riscv: adjust the indent Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com> |
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| 2020-02-24 | Zong Li | riscv: allocate a complete page size for each page... Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com> |
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| 2020-02-20 | Damien Le Moal | riscv: Fix gitignore Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com> |
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| 2020-02-18 | Anup Patel | RISC-V: Don't enable all interrupts in trap_init() Tested-by: Palmer Dabbelt <palmerdabbelt@google.com> [QMEU... Reviewed-by: Palmer Dabbelt <palmerdabbelt@google.com> Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com> |
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| 2020-02-18 | Greentime Hu | riscv: set pmp configuration if kernel is running in... Reviewed-by: Palmer Dabbelt <palmerdabbelt@google.com> Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com> |
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| 2020-01-29 | Yash Shah | riscv: dts: Add DT support for SiFive FU540 GPIO driver Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com> |
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| 2020-01-23 | Zong Li | riscv: mm: add support for CONFIG_DEBUG_VIRTUAL Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com> |
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| 2020-01-22 | Olof Johansson | riscv: keep 32-bit kernel to 32-bit phys_addr_t Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com> |
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| 2020-01-22 | Nick Hu | kasan: Add riscv to KASAN documentation. Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com> |
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| 2020-01-22 | Nick Hu | riscv: Add KASAN support Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com> |
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| 2020-01-22 | Nick Hu | kasan: No KASAN's memmove check if archs don't have it. Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com> |
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| 2019-05-17 | Andreas Schwab | riscv: fix locking violation in page fault handler Signed-off-by: Palmer Dabbelt <palmer@sifive.com> |
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| 2019-05-17 | Yash Shah | RISC-V: sifive_l2_cache: Add L2 cache controller driver... Signed-off-by: Palmer Dabbelt <palmer@sifive.com> |
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| 2019-05-17 | Yash Shah | RISC-V: Add DT documentation for SiFive L2 Cache Controller Signed-off-by: Palmer Dabbelt <palmer@sifive.com> |
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| 2019-05-17 | Palmer Dabbelt | RISC-V: Avoid using invalid intermediate translations Signed-off-by: Palmer Dabbelt <palmer@sifive.com> |
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| 2019-05-17 | Vincent Chen | riscv: Support BUG() in kernel module Signed-off-by: Palmer Dabbelt <palmer@sifive.com> |
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| 2019-05-17 | Vincent Chen | riscv: Add the support for c.ebreak check in is_valid_bugaddr() Signed-off-by: Palmer Dabbelt <palmer@sifive.com> |
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| 2019-05-17 | Vincent Chen | riscv: support trap-based WARN() Signed-off-by: Palmer Dabbelt <palmer@sifive.com> |
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| 2019-05-17 | Gary Guo | riscv: fix sbi_remote_sfence_vma{,_asid}. Signed-off-by: Palmer Dabbelt <palmer@sifive.com> |
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| 2019-05-17 | Gary Guo | riscv: move switch_mm to its own file Signed-off-by: Palmer Dabbelt <palmer@sifive.com> |
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| 2019-05-17 | Gary Guo | riscv: move flush_icache_{all,mm} to cacheflush.c Signed-off-by: Palmer Dabbelt <palmer@sifive.com> |
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| 2019-05-17 | Anup Patel | tty: Don't force RISCV SBI console as preferred console Signed-off-by: Palmer Dabbelt <palmer@sifive.com> |
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| 2019-05-17 | Anup Patel | RISC-V: Access CSRs using CSR numbers Signed-off-by: Palmer Dabbelt <palmer@sifive.com> |
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| 2019-05-17 | Anup Patel | RISC-V: Add interrupt related SCAUSE defines in asm... Signed-off-by: Palmer Dabbelt <palmer@sifive.com> |
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| 2019-05-17 | Anup Patel | RISC-V: Use tabs to align macro values in asm/csr.h Signed-off-by: Palmer Dabbelt <palmer@sifive.com> |
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| 2019-05-17 | Atish Patra | RISC-V: Fix minor checkpatch issues. Signed-off-by: Palmer Dabbelt <palmer@sifive.com> |
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| 2019-05-17 | Atish Patra | RISC-V: Support nr_cpus command line option. Signed-off-by: Palmer Dabbelt <palmer@sifive.com> |
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| 2019-04-30 | Atish Patra | RISC-V: Implement nosmp commandline option. Signed-off-by: Palmer Dabbelt <palmer@sifive.com> |
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| 2019-04-30 | Atish Patra | RISC-V: Add RISC-V specific arch_match_cpu_phys_id Signed-off-by: Palmer Dabbelt <palmer@sifive.com> |
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| 2019-04-29 | Nick Desaulniers | riscv: vdso: drop unnecessary cc-ldoption Signed-off-by: Palmer Dabbelt <palmer@sifive.com> |
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| 2019-04-25 | Christoph Hellwig | riscv: call pm_power_off from machine_halt / machine_power_off Signed-off-by: Palmer Dabbelt <palmer@sifive.com> |
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| 2019-04-25 | Christoph Hellwig | riscv: print the unexpected interrupt cause Signed-off-by: Palmer Dabbelt <palmer@sifive.com> |
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| 2019-04-25 | Christoph Hellwig | riscv: remove duplicate macros from ptrace.h Signed-off-by: Palmer Dabbelt <palmer@sifive.com> |
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| 2019-04-25 | Christoph Hellwig | riscv: remove unreachable !HAVE_FUNCTION_GRAPH_RET_ADDR_PTR... Signed-off-by: Palmer Dabbelt <palmer@sifive.com> |
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| 2019-04-25 | Christoph Hellwig | riscv: cleanup the parse_dtb calling conventions Signed-off-by: Palmer Dabbelt <palmer@sifive.com> |
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| 2019-04-25 | Christoph Hellwig | riscv: simplify the stack pointer setup in head.S Signed-off-by: Palmer Dabbelt <palmer@sifive.com> |
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| 2019-04-25 | Christoph Hellwig | riscv: clear all pending interrupts when booting Signed-off-by: Palmer Dabbelt <palmer@sifive.com> |
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| 2019-04-25 | Christoph Hellwig | riscv: remove CONFIG_RISCV_ISA_A Signed-off-by: Palmer Dabbelt <palmer@sifive.com> |
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| 2019-04-25 | Christoph Hellwig | riscv: remove unreachable big endian code Signed-off-by: Palmer Dabbelt <palmer@sifive.com> |
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| 2019-04-25 | Christoph Hellwig | riscv: turn mm_segment_t into a struct Signed-off-by: Palmer Dabbelt <palmer@sifive.com> |
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| 2019-04-25 | Christoph Hellwig | riscv: use asm-generic/extable.h Signed-off-by: Palmer Dabbelt <palmer@sifive.com> |
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| 2019-04-25 | Guo Ren | riscv/signal: Fixup additional syscall restarting Signed-off-by: Palmer Dabbelt <palmer@sifive.com> |
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| 2019-04-10 | Anup Patel | RISC-V: Fix Maximum Physical Memory 2GiB option for... Signed-off-by: Palmer Dabbelt <palmer@sifive.com> |
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| 2019-04-10 | Paul Walmsley | dt-bindings: clock: sifive: add FU540-C000 PRCI clock... Signed-off-by: Palmer Dabbelt <palmer@sifive.com> |
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| 2019-04-09 | Anup Patel | RISC-V: Add separate defconfig for 32bit systems Signed-off-by: Palmer Dabbelt <palmer@sifive.com> |
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| 2019-03-29 | Joe Perches | RISC-V: Use IS_ENABLED(CONFIG_CMODEL_MEDLOW) Signed-off-by: Palmer Dabbelt <palmer@sifive.com> |
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| 2019-03-29 | Anup Patel | RISC-V: Fix FIXMAP_TOP to avoid overlap with VMALLOC... Signed-off-by: Palmer Dabbelt <palmer@sifive.com> |
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