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drm/xe: Remove gen-based mmio offsets from hw engine init
2023-12-19 Matt Roperdrm/xe: Remove gen-based mmio offsets from hw engine...
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
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2023-10-25 Matt Roperdrm/i915/mcr: Hold GT forcewake during steering operations
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
...msgid/20231019170241.2102037-2-matthew.d.roper@intel.com
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2023-09-21 Matt Roperdrm/i915/xe2lpd: Add DC state support
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
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2023-09-21 Matt Roperdrm/i915/xe2lpd: Don't try to program PLANE_AUX_DIST
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
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2023-09-21 Matt Roperdrm/i915/xe2lpd: FBC is now supported on all pipes
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
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2023-09-08 Matt Roperdrm/i915/display: Apply workarounds during display...
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
...msgid/20230906234732.3728630-10-matthew.d.roper@intel.com
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2023-09-08 Matt Roperdrm/i915/display: Extract display workarounds from...
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
...msgid/20230907001009.3732474-2-matthew.d.roper@intel.com
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2023-09-08 Matt Roperdrm/i915/adlp: Stop calling gen12lp_init_clock_gating()
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
...msgid/20230906234732.3728630-8-matthew.d.roper@intel.com
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2023-09-08 Matt Roperdrm/i915: Stop forcing clock gating init for future...
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
...msgid/20230906234732.3728630-7-matthew.d.roper@intel.com
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2023-09-07 Matt Roperdrm/i915/mtl: Drop Wa_14017240301
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
...msgid/20230907000354.3729827-2-matthew.d.roper@intel.com
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2023-08-22 Matt Roperdrm/i915/display: Eliminate IS_METEORLAKE checks
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
...msgid/20230821180619.650007-19-matthew.d.roper@intel.com
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2023-08-22 Matt Roperdrm/i915: Eliminate IS_MTL_DISPLAY_STEP
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
...msgid/20230821180619.650007-17-matthew.d.roper@intel.com
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2023-08-21 Matt Roperdrm/i915: Replace several IS_METEORLAKE with proper...
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
...msgid/20230821180619.650007-20-matthew.d.roper@intel.com
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2023-08-21 Matt Roperdrm/i915/mtl: Eliminate subplatforms
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
...msgid/20230821180619.650007-18-matthew.d.roper@intel.com
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2023-08-21 Matt Roperdrm/i915: Eliminate IS_MTL_MEDIA_STEP
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
...msgid/20230821180619.650007-16-matthew.d.roper@intel.com
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2023-08-21 Matt Roperdrm/i915: Eliminate IS_MTL_GRAPHICS_STEP
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
...msgid/20230821180619.650007-15-matthew.d.roper@intel.com
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2023-08-21 Matt Roperdrm/i915/xelpg: Call Xe_LPG workaround functions based...
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
...msgid/20230821180619.650007-14-matthew.d.roper@intel.com
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2023-08-21 Matt Roperdrm/i915/xelpmp: Don't assume workarounds extend to...
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
...msgid/20230821180619.650007-13-matthew.d.roper@intel.com
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2023-08-21 Matt Roperdrm/i915: Consolidate condition for Wa_22011802037
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
...msgid/20230821180619.650007-12-matthew.d.roper@intel.com
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2023-08-17 Matt Roperdrm/i915: Eliminate has_4tile feature flag
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
...msgid/20230810234618.3738870-4-matthew.d.roper@intel.com
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2023-08-17 Matt Roperdrm/i915/selftest: Simplify Y-major tiling in blit...
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
...msgid/20230810234618.3738870-3-matthew.d.roper@intel.com
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2023-08-17 Matt Roperdrm/i915/dg2: Drop Wa_16011777198
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
...msgid/20230816214824.548575-2-matthew.d.roper@intel.com
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2023-08-17 Matt Roperdrm/i915: Tidy workaround definitions
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
...msgid/20230816214201.534095-11-matthew.d.roper@intel.com
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2023-08-17 Matt Roperdrm/i915/dg2: Drop pre-production GT workarounds
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
...msgid/20230816214201.534095-10-matthew.d.roper@intel.com
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2023-08-17 Matt Roperdrm/i915/dg2: Drop pre-production display workarounds
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
...msgid/20230816214201.534095-9-matthew.d.roper@intel.com
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2023-08-17 Matt Roperdrm/i915/dg2: Recognize pre-production hardware
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
...msgid/20230816214201.534095-8-matthew.d.roper@intel.com
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2023-06-23 Matt Roperdrm/i915: Extend Wa_14015795083 platforms
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
...msgid/20230616225041.3922719-1-matthew.d.roper@intel.com
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2023-06-07 Matt Roperdrm/i915/display: Include of display limits doesn't...
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
...msgid/20230607150946.1996087-1-matthew.d.roper@intel.com
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2023-06-05 Matt Roperdrm/i915: Fix error handling if driver creation fails...
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
...msgid/20230601173804.557756-1-matthew.d.roper@intel.com
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2023-06-05 Matt Roperdrm/i915/display: Extract display init from intel_device_inf...
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
...msgid/20230602181450.1151368-1-matthew.d.roper@intel.com
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2023-05-24 Matt Roperdrm/i915/display: Move feature test macros to intel_display_...
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
...msgid/20230523195609.73627-7-matthew.d.roper@intel.com
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2023-05-24 Matt Roperdrm/i915/display: Handle GMD_ID identification in display...
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
...msgid/20230523195609.73627-6-matthew.d.roper@intel.com
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2023-05-24 Matt Roperdrm/i915/display: Make display responsible for probing...
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
...msgid/20230523195609.73627-5-matthew.d.roper@intel.com
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2023-05-24 Matt Roperdrm/i915/display: Move display runtime info to display...
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
...msgid/20230523195609.73627-4-matthew.d.roper@intel.com
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2023-05-24 Matt Roperdrm/i915: Convert INTEL_INFO()->display to a pointer
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
...msgid/20230523195609.73627-3-matthew.d.roper@intel.com
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2023-05-24 Matt Roperdrm/i915/display: Move display device info to header...
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
...msgid/20230523195609.73627-2-matthew.d.roper@intel.com
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2023-04-19 Matt Roperdrm/i915/mtl: Re-use ADL-P's "DC off" power well
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
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2023-04-19 Matt Roperdrm/i915: Use separate "DC off" power well for ADL...
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
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2023-03-28 Matt Roperdrm/i915: Check for unreliable MMIO during forcewake
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
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2023-03-28 Matt Roperdrm/i915: Sanitycheck MMIO access early in driver load
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
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2023-02-28 Matt Roperdrm/i915: Stop whitelisting CS_CTX_TIMESTAMP on Xe_HP...
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
...msgid/20230224002300.3578985-2-matthew.d.roper@intel.com
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2023-02-28 Matt Roperdrm/i915: Whitelist COMMON_SLICE_CHICKEN3 for UMD access
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
...msgid/20230224002300.3578985-1-matthew.d.roper@intel.com
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2023-02-27 Matt Roperdrm/i915/gen12: Update combo PHY init sequence
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
...msgid/20230221201836.2886794-1-matthew.d.roper@intel.com
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2023-02-24 Matt Roperdrm/i915/mtl: Add engine TLB invalidation
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
...msgid/20230224012009.3594691-1-matthew.d.roper@intel.com
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2023-02-23 Matt Roperdrm/i915/xelpmp: Consider GSI offset when doing MCR...
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
...msgid/20230214001906.1477370-1-matthew.d.roper@intel.com
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2023-02-15 Matt Roperdrm/i915/xelpmp: Consider GSI offset when doing MCR...
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
...msgid/20230214001906.1477370-1-matthew.d.roper@intel.com
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2023-02-15 Matt Roperdrm/i915/pvc: Annotate two more workaround/tuning registers...
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
...msgid/20230201222831.608281-1-matthew.d.roper@intel.com
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2023-02-14 Matt Roperdrm/i915/gen11: Wa_1408615072/Wa_1407596294 should...
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
...msgid/20230201222831.608281-2-matthew.d.roper@intel.com
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2023-02-10 Matt Roperdrm/i915/xehp: LNCF/LBCF workarounds should be on the...
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
...msgid/20230209232228.859317-1-matthew.d.roper@intel.com
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2023-02-08 Matt Roperdrm/i915/dg2: Drop one PCI ID
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
...msgid/20230208200905.680865-1-matthew.d.roper@intel.com
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2023-02-08 Matt Roperdrm/i915/gen11: Wa_1408615072/Wa_1407596294 should...
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
...msgid/20230201222831.608281-2-matthew.d.roper@intel.com
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2023-02-08 Matt Roperdrm/i915/pvc: Annotate two more workaround/tuning registers...
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
...msgid/20230201222831.608281-1-matthew.d.roper@intel.com
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2023-01-30 Matt Roperdrm/i915/dg1: Drop final use of IS_DG1_GRAPHICS_STEP
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
...msgid/20230127224313.4042331-4-matthew.d.roper@intel.com
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2023-01-30 Matt Roperdrm/i915/dg1: Drop support for pre-production steppings
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
...msgid/20230127224313.4042331-3-matthew.d.roper@intel.com
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2023-01-30 Matt Roperdrm/i915/tgl: Drop support for pre-production steppings
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
...msgid/20230127224313.4042331-2-matthew.d.roper@intel.com
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2023-01-26 Matt Roperdrm/i915/xehp: Annotate a couple more workaround registers...
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
...msgid/20230125234159.3015385-3-matthew.d.roper@intel.com
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2023-01-26 Matt Roperdrm/i915/mtl: Correct implementation of Wa_18018781329
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
...msgid/20230125234159.3015385-2-matthew.d.roper@intel.com
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2023-01-26 Matt Roperdrm/i915/xehp: GAM registers don't need to be re-applied...
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
...msgid/20230125234159.3015385-1-matthew.d.roper@intel.com
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2023-01-18 Matt Roperdrm/i915: Move/adjust register definitions related...
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
...msgid/20230117202627.4134579-1-matthew.d.roper@intel.com
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2023-01-06 Matt Roperdrm/i915/mtl: Add initial gt workarounds
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
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2022-12-15 Matt Roperdrm/i915/dg2: Return Wa_22012654132 to just specific...
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
...msgid/20221213234119.2963317-1-matthew.d.roper@intel.com
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2022-12-09 Matt Roperdrm/i915/gt: Correct kerneldoc for intel_gt_mcr_wait_for_reg()
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
...msgid/20221128233014.4000136-2-matthew.d.roper@intel.com
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2022-12-05 Matt Roperdrm/i915/gen12: Apply recommended L3 hashing mask
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
...msgid/20221201222210.344152-1-matthew.d.roper@intel.com
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2022-12-05 Matt Roperdrm/i915/mtl: Check full IP version when applying hw...
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
...msgid/20221202223528.714491-1-matthew.d.roper@intel.com
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2022-12-02 Matt Roperdrm/i915/mtl: Add hardware-level lock for steering
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
...msgid/20221128233014.4000136-5-matthew.d.roper@intel.com
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2022-12-01 Matt Roperdrm/i915/mcr: Hold forcewake and MCR lock over PPAT...
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
...msgid/20221130155852.19601-1-matthew.d.roper@intel.com
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2022-11-30 Matt Roperdrm/i915/gt: Add dedicated MCR lock
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
...msgid/20221128233014.4000136-4-matthew.d.roper@intel.com
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2022-11-30 Matt Roperdrm/i915/gt: Pass gt rather than uncore to lowest-level...
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
...msgid/20221128233014.4000136-3-matthew.d.roper@intel.com
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2022-11-30 Matt Roperdrm/i915/gt: Correct kerneldoc for intel_gt_mcr_wait_for_reg()
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
...msgid/20221128233014.4000136-2-matthew.d.roper@intel.com
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2022-11-23 Matt Roperdrm/i915/gt: Manage uncore->lock while waiting on MCR...
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
...msgid/20221117173358.1980230-1-matthew.d.roper@intel.com
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2022-11-18 Matt Roperdrm/i915/gt: Manage uncore->lock while waiting on MCR...
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
...msgid/20221117173358.1980230-1-matthew.d.roper@intel.com
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2022-11-18 Matt Roperdrm/i915/dg2: Drop force_probe requirement
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
...msgid/20221109001328.732000-1-matthew.d.roper@intel.com
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2022-10-29 Matt Roperdrm/i915/mtl: Add missing steering table terminators
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
...msgid/20221028224022.964997-1-matthew.d.roper@intel.com
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2022-10-21 Matt Roperdrm/i915/xelpg: Fix write to MTL_MCR_SELECTOR
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
...msgid/20221019222437.3035182-1-matthew.d.roper@intel.com
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2022-10-18 Matt Roperdrm/i915/pvc: Update forcewake domain for CCS register...
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
...msgid/20221014233004.1053678-1-matthew.d.roper@intel.com
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2022-10-17 Matt Roperdrm/i915/xelpmp: Add multicast steering for media GT
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
...msgid/20221014230239.1023689-15-matthew.d.roper@intel.com
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2022-10-17 Matt Roperdrm/i915/xelpg: Add multicast steering
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
...msgid/20221014230239.1023689-14-matthew.d.roper@intel.com
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2022-10-17 Matt Roperdrm/i915: Define multicast registers as a new type
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
...msgid/20221014230239.1023689-13-matthew.d.roper@intel.com
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2022-10-17 Matt Roperdrm/i915/gt: Add MCR-specific workaround initializers
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
...msgid/20221014230239.1023689-12-matthew.d.roper@intel.com
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2022-10-17 Matt Roperdrm/i915/guc: Handle save/restore of MCR registers...
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
...msgid/20221014230239.1023689-11-matthew.d.roper@intel.com
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2022-10-17 Matt Roperdrm/i915/gt: Always use MCR functions on multicast...
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
...msgid/20221014230239.1023689-10-matthew.d.roper@intel.com
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2022-10-17 Matt Roperdrm/i915: Define MCR registers explicitly
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
...msgid/20221014230239.1023689-9-matthew.d.roper@intel.com
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2022-10-17 Matt Roperdrm/i915/gt: Add intel_gt_mcr_wait_for_reg_fw()
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
...msgid/20221014230239.1023689-8-matthew.d.roper@intel.com
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2022-10-17 Matt Roperdrm/i915/xehp: Check for faults on primary GAM
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
...msgid/20221014230239.1023689-7-matthew.d.roper@intel.com
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2022-10-17 Matt Roperdrm/i915/gt: Add intel_gt_mcr_multicast_rmw() operation
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
...msgid/20221014230239.1023689-6-matthew.d.roper@intel.com
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2022-10-17 Matt Roperdrm/i915/gt: Correct prefix on a few registers
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
...msgid/20221014230239.1023689-5-matthew.d.roper@intel.com
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2022-10-17 Matt Roperdrm/i915/gt: Drop a few unused register definitions
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
...msgid/20221014230239.1023689-4-matthew.d.roper@intel.com
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2022-10-17 Matt Roperdrm/i915/xehp: Create separate reg definitions for...
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
...msgid/20221014230239.1023689-3-matthew.d.roper@intel.com
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2022-10-17 Matt Roperdrm/i915/gen8: Create separate reg definitions for...
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
...msgid/20221014230239.1023689-2-matthew.d.roper@intel.com
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2022-10-04 Matt Roperdrm/i915: Document and future-proof preemption control...
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
...msgid/20220907212410.22623-1-matthew.d.roper@intel.com
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2022-09-30 Matt Roperdrm/i915/mtl: Define engine context layouts
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
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2022-09-24 Matt Roperdrm/i915: Read graphics/media/display arch version...
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
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2022-09-21 Matt Roperdrm/i915: Split GAM and MSLICE steering
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
...msgid/20220916014345.3317739-1-matthew.d.roper@intel.com
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2022-09-19 Matt Roperdrm/i915/mtl: Add MTL forcewake support
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
...msgid/20220910001631.1986601-1-matthew.d.roper@intel.com
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2022-09-12 Matt Roperdrm/i915/mtl: Hook up interrupts for standalone media
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
...msgid/20220906234934.3655440-15-matthew.d.roper@intel.com
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2022-09-12 Matt Roperdrm/i915/mtl: Use primary GT's irq lock for media GT
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
...msgid/20220906234934.3655440-14-matthew.d.roper@intel.com
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2022-09-12 Matt Roperdrm/i915/xelpmp: Expose media as another GT
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
...msgid/20220906234934.3655440-13-matthew.d.roper@intel.com
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2022-09-12 Matt Roperdrm/i915/mtl: Add gsi_offset when emitting aux table...
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
...msgid/20220906234934.3655440-12-matthew.d.roper@intel.com
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2022-09-12 Matt Roperdrm/i915/uncore: Add GSI offset to uncore
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
...msgid/20220908224550.821257-1-matthew.d.roper@intel.com
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2022-09-12 Matt Roperdrm/i915: Handle each GT on init/release and suspend...
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
...msgid/20220906234934.3655440-10-matthew.d.roper@intel.com
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