2021-04-07 | Matt Roper | drm/i915/display: Eliminate IS_GEN9_{BC,LP} Signed-off-by: Matt Roper <matthew.d.roper@intel.com> ...msgid/20210407203945.1432531-1-matthew.d.roper@intel.com |
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2021-03-23 | Matt Roper | drm/i915/display: Simplify GLK display version tests Signed-off-by: Matt Roper <matthew.d.roper@intel.com> ...msgid/20210322233840.4056851-1-matthew.d.roper@intel.com |
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2021-03-23 | Matt Roper | drm/i915: Convert INTEL_GEN() to DISPLAY_VER() as appropriat... Signed-off-by: Matt Roper <matthew.d.roper@intel.com> ...msgid/20210320044245.3920043-6-matthew.d.roper@intel.com |
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2021-03-23 | Matt Roper | drm/i915: Convert INTEL_GEN() to DISPLAY_VER() as appropriat... Signed-off-by: Matt Roper <matthew.d.roper@intel.com> ...msgid/20210320044245.3920043-5-matthew.d.roper@intel.com |
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2021-03-23 | Matt Roper | drm/i915/display: Eliminate most usage of INTEL_GEN() Signed-off-by: Matt Roper <matthew.d.roper@intel.com> ...msgid/20210320044245.3920043-4-matthew.d.roper@intel.com |
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2021-03-23 | Matt Roper | drm/i915: Add DISPLAY_VER() and related macros Signed-off-by: Matt Roper <matthew.d.roper@intel.com> ...msgid/20210320044245.3920043-3-matthew.d.roper@intel.com |
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2021-03-23 | Matt Roper | drm/i915/display: Convert gen5/gen6 tests to IS_IRONLAKE... Signed-off-by: Matt Roper <matthew.d.roper@intel.com> ...msgid/20210320044245.3920043-2-matthew.d.roper@intel.com |
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2021-02-13 | Matt Roper | drm/i915: Try to detect sudden loss of MMIO access Signed-off-by: Matt Roper <matthew.d.roper@intel.com> ...msgid/20210212211925.3418280-2-matthew.d.roper@intel.com |
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2021-02-13 | Matt Roper | drm/i915: FPGA_DBG is display-specific Signed-off-by: Matt Roper <matthew.d.roper@intel.com> ...msgid/20210212222049.3516344-1-matthew.d.roper@intel.com |
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2021-02-01 | Matt Roper | drm/i915/adl_s: Re-use TGL GuC/HuC firmware Signed-off-by: Matt Roper <matthew.d.roper@intel.com> |
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2021-02-01 | Matt Roper | drm/i915/adl_s: Update PHY_MISC programming Signed-off-by: Matt Roper <matthew.d.roper@intel.com> |
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2021-01-26 | Matt Roper | drm/i915/adl_s: Update combo PHY master/slave relationships Signed-off-by: Matt Roper <matthew.d.roper@intel.com> |
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2021-01-12 | Matt Roper | drm/i915/dg1: Update voltage swing tables for DP Signed-off-by: Matt Roper <matthew.d.roper@intel.com> ...msgid/20210108222528.1954514-1-matthew.d.roper@intel.com |
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2021-01-06 | Matt Roper | drm/i915/rkl: Add DP vswing programming tables Signed-off-by: Matt Roper <matthew.d.roper@intel.com> ...msgid/20201218040535.45492-1-matthew.d.roper@intel.com |
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2021-01-01 | Matt Roper | drm/i915: Clarify error message on failed workaround Signed-off-by: Matt Roper <matthew.d.roper@intel.com> ...msgid/20201231191103.854519-1-matthew.d.roper@intel.com |
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2020-10-16 | Matt Roper | drm/i915/rkl: Add new cdclk table Signed-off-by: Matt Roper <matthew.d.roper@intel.com> ...msgid/20201015220038.271740-1-matthew.d.roper@intel.com |
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2020-10-10 | Matt Roper | drm/i915: Update gen12 multicast register ranges Signed-off-by: Matt Roper <matthew.d.roper@intel.com> ...msgid/20201009194442.3668677-4-matthew.d.roper@intel.com |
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2020-10-10 | Matt Roper | drm/i915: Update gen12 forcewake table Signed-off-by: Matt Roper <matthew.d.roper@intel.com> ...msgid/20201009194442.3668677-3-matthew.d.roper@intel.com |
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2020-10-10 | Matt Roper | drm/i915: Rename FORCEWAKE_BLITTER to FORCEWAKE_GT Signed-off-by: Matt Roper <matthew.d.roper@intel.com> ...msgid/20201009194442.3668677-2-matthew.d.roper@intel.com |
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2020-10-07 | Matt Roper | drm/i915/dg1: provide port/phy mapping for vbt Signed-off-by: Matt Roper <matthew.d.roper@intel.com> |
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2020-10-07 | Matt Roper | drm/i915/dg1: Update comp master/slave relationships... Signed-off-by: Matt Roper <matthew.d.roper@intel.com> |
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2020-10-07 | Matt Roper | drm/i915/dg1: Don't program PHY_MISC for PHY-C and... Signed-off-by: Matt Roper <matthew.d.roper@intel.com> |
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2020-10-07 | Matt Roper | drm/i915/dg1: Initialize RAWCLK properly Signed-off-by: Matt Roper <matthew.d.roper@intel.com> |
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2020-10-05 | Matt Roper | drm/i915/dg1: Wait for pcode/uncore handshake at startup Signed-off-by: Matt Roper <matthew.d.roper@intel.com> |
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2020-08-19 | Matt Roper | drm/i915: Update bw_buddy pagemask table Signed-off-by: Matt Roper <matthew.d.roper@intel.com> ...msgid/20200612204734.3674650-1-matthew.d.roper@intel.com |
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2020-08-17 | Matt Roper | drm/i915/kbl: Fix revision ID checks Signed-off-by: Matt Roper <matthew.d.roper@intel.com> ...msgid/20200811032105.2819370-1-matthew.d.roper@intel.com |
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2020-08-17 | Matt Roper | Revert "drm/i915/rkl: Add Wa_14011224835 for PHY B... Signed-off-by: Matt Roper <matthew.d.roper@intel.com> ...msgid/20200804044024.1931170-1-matthew.d.roper@intel.com |
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2020-08-17 | Matt Roper | drm/i915: Update bw_buddy pagemask table Signed-off-by: Matt Roper <matthew.d.roper@intel.com> ...msgid/20200612204734.3674650-1-matthew.d.roper@intel.com |
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2020-08-17 | Matt Roper | drm/i915/rkl: Add Wa_14011224835 for PHY B initialization Signed-off-by: Matt Roper <matthew.d.roper@intel.com> ...msgid/20200716220551.2730644-6-matthew.d.roper@intel.com |
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2020-08-17 | Matt Roper | drm/i915/rkl: Handle HTI Signed-off-by: Matt Roper <matthew.d.roper@intel.com> ...msgid/20200716220551.2730644-5-matthew.d.roper@intel.com |
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2020-08-17 | Matt Roper | drm/i915/rkl: Add DPLL4 support Signed-off-by: Matt Roper <matthew.d.roper@intel.com> ...msgid/20200716220551.2730644-4-matthew.d.roper@intel.com |
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2020-08-17 | Matt Roper | drm/i915/rkl: Add initial workarounds Signed-off-by: Matt Roper <matthew.d.roper@intel.com> ...msgid/20200716220551.2730644-3-matthew.d.roper@intel.com |
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2020-08-17 | Matt Roper | drm/i915/rkl: Handle new DPCLKA_CFGCR0 layout Signed-off-by: Matt Roper <matthew.d.roper@intel.com> ...msgid/20200716220551.2730644-2-matthew.d.roper@intel.com |
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2020-06-26 | Matt Roper | drm/i915: Extend Wa_14010685332 to all ICP+ PCH's Signed-off-by: Matt Roper <matthew.d.roper@intel.com> ...msgid/20200617180006.4130501-1-matthew.d.roper@intel.com |
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2020-06-09 | Matt Roper | drm/i915/rkl: Update TGP's pin mapping when paired... Signed-off-by: Matt Roper <matthew.d.roper@intel.com> ...msgid/20200606025740.3308880-4-matthew.d.roper@intel.com |
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2020-06-09 | Matt Roper | drm/i915/rkl: RKL uses ABOX0 for pixel transfers Signed-off-by: Matt Roper <matthew.d.roper@intel.com> ...msgid/20200606025740.3308880-2-matthew.d.roper@intel.com |
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2020-06-06 | Matt Roper | drm/i915: Restore DP-E to VBT mapping table Cc: Matt Roper <matthew.d.roper@intel.com> Signed-off-by: Matt Roper <matthew.d.roper@intel.com> ...msgid/20200606031803.3309624-1-matthew.d.roper@intel.com |
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2020-06-04 | Matt Roper | drm/i915/rkl: Don't try to access transcoder D Signed-off-by: Matt Roper <matthew.d.roper@intel.com> ...msgid/20200603211529.3005059-10-matthew.d.roper@intel.com |
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2020-06-04 | Matt Roper | drm/i915/rkl: Setup ports/phys Signed-off-by: Matt Roper <matthew.d.roper@intel.com> ...msgid/20200603211529.3005059-6-matthew.d.roper@intel.com |
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2020-06-04 | Matt Roper | drm/i915/rkl: Handle comp master/slave relationships... Signed-off-by: Matt Roper <matthew.d.roper@intel.com> ...msgid/20200603211529.3005059-12-matthew.d.roper@intel.com |
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2020-06-04 | Matt Roper | drm/i915/rkl: Add DDC pin mapping Signed-off-by: Matt Roper <matthew.d.roper@intel.com> ...msgid/20200603211529.3005059-9-matthew.d.roper@intel.com |
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2020-06-04 | Matt Roper | drm/i915/rkl: Set transcoder mask properly Signed-off-by: Matt Roper <matthew.d.roper@intel.com> ...msgid/20200603211529.3005059-2-matthew.d.roper@intel.com |
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2020-05-20 | Matt Roper | drm/i915/rkl: RKL only uses PHY_MISC for PHY's A and B Signed-off-by: Matt Roper <matthew.d.roper@intel.com> ...msgid/20200504225227.464666-11-matthew.d.roper@intel.com |
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2020-05-20 | Matt Roper | drm/i915/rkl: Add power well support Signed-off-by: Matt Roper <matthew.d.roper@intel.com> ...msgid/20200504225227.464666-9-matthew.d.roper@intel.com |
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2020-05-20 | Matt Roper | drm/i915/rkl: Limit number of universal planes to 5 Signed-off-by: Matt Roper <matthew.d.roper@intel.com> ...msgid/20200504225227.464666-8-matthew.d.roper@intel.com |
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2020-05-20 | Matt Roper | drm/i915/rkl: Update memory bandwidth parameters Signed-off-by: Matt Roper <matthew.d.roper@intel.com> ...msgid/20200504225227.464666-7-matthew.d.roper@intel.com |
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2020-05-20 | Matt Roper | x86/gpu: add RKL stolen memory support Signed-off-by: Matt Roper <matthew.d.roper@intel.com> ...msgid/20200504225227.464666-3-matthew.d.roper@intel.com |
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2020-05-20 | Matt Roper | drm/i915/rkl: Add PCH support Signed-off-by: Matt Roper <matthew.d.roper@intel.com> ...msgid/20200504225227.464666-6-matthew.d.roper@intel.com |
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2020-05-20 | Matt Roper | drm/i915/rkl: Load DMC firmware for Rocket Lake Signed-off-by: Matt Roper <matthew.d.roper@intel.com> ...msgid/20200504225227.464666-5-matthew.d.roper@intel.com |
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2020-05-20 | Matt Roper | drm/i915/rkl: Re-use TGL GuC/HuC firmware Signed-off-by: Matt Roper <matthew.d.roper@intel.com> ...msgid/20200504225227.464666-4-matthew.d.roper@intel.com |
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2020-05-20 | Matt Roper | drm/i915/rkl: Add RKL platform info and PCI ids Signed-off-by: Matt Roper <matthew.d.roper@intel.com> ...msgid/20200504225227.464666-2-matthew.d.roper@intel.com |
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2020-05-05 | Matt Roper | drm/i915/icp: Add Wa_14010685332 Signed-off-by: Matt Roper <matthew.d.roper@intel.com> ...msgid/20200501213701.371443-1-matthew.d.roper@intel.com |
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2020-04-28 | Matt Roper | drm/i915: Use proper fault mask in interrupt postinstall too Signed-off-by: Matt Roper <matthew.d.roper@intel.com> ...msgid/20200424231423.4065231-1-matthew.d.roper@intel.com |
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2020-04-27 | Matt Roper | drm/i915: Use proper fault mask in interrupt postinstall too Signed-off-by: Matt Roper <matthew.d.roper@intel.com> ...msgid/20200424231423.4065231-1-matthew.d.roper@intel.com |
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2020-04-21 | Matt Roper | drm/i915: Use single set of AUX powerwell ops for gen11+ Signed-off-by: Matt Roper <matthew.d.roper@intel.com> ...msgid/20200415233435.3064257-2-matthew.d.roper@intel.com |
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2020-04-20 | Matt Roper | drm/i915/tgl: TBT AUX should use TC power well ops Signed-off-by: Matt Roper <matthew.d.roper@intel.com> ...msgid/20200415233435.3064257-1-matthew.d.roper@intel.com |
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2020-04-20 | Matt Roper | drm/i915/tgl: Add Wa_14010477008:tgl Signed-off-by: Matt Roper <matthew.d.roper@intel.com> ...msgid/20200414211118.2787489-3-matthew.d.roper@intel.com |
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2020-04-17 | Matt Roper | drm/i915/tgl: TBT AUX should use TC power well ops Signed-off-by: Matt Roper <matthew.d.roper@intel.com> ...msgid/20200415233435.3064257-1-matthew.d.roper@intel.com |
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2020-04-15 | Matt Roper | drm/i915/tgl: Initialize multicast register steering... Signed-off-by: Matt Roper <matthew.d.roper@intel.com> ...msgid/20200414211118.2787489-4-matthew.d.roper@intel.com |
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2020-04-15 | Matt Roper | drm/i915/tgl: Extend Wa_1409767108:tgl to B0 stepping Signed-off-by: Matt Roper <matthew.d.roper@intel.com> ...msgid/20200414211118.2787489-2-matthew.d.roper@intel.com |
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2020-04-15 | Matt Roper | drm/i915/tgl: Add Wa_14010477008:tgl Signed-off-by: Matt Roper <matthew.d.roper@intel.com> ...msgid/20200414211118.2787489-3-matthew.d.roper@intel.com |
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2020-03-16 | Matt Roper | drm/i915: Handle all MCR ranges Signed-off-by: Matt Roper <matthew.d.roper@intel.com> ...msgid/20200311162300.1838847-2-matthew.d.roper@intel.com |
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2020-03-13 | Matt Roper | drm/i915: Add Wa_1605460711 / Wa_1408767742 to ICL... Signed-off-by: Matt Roper <matthew.d.roper@intel.com> ...msgid/20200311162300.1838847-7-matthew.d.roper@intel.com |
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2020-03-13 | Matt Roper | drm/i915: Apply Wa_1406680159:icl,ehl as an engine... Signed-off-by: Matt Roper <matthew.d.roper@intel.com> ...msgid/20200311162300.1838847-6-matthew.d.roper@intel.com |
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2020-03-13 | Matt Roper | drm/i915: Add Wa_1406306137:icl,ehl Signed-off-by: Matt Roper <matthew.d.roper@intel.com> ...msgid/20200311162300.1838847-5-matthew.d.roper@intel.com |
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2020-03-13 | Matt Roper | drm/i915: Add Wa_1604278689:icl,ehl Signed-off-by: Matt Roper <matthew.d.roper@intel.com> ...msgid/20200311162300.1838847-4-matthew.d.roper@intel.com |
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2020-03-13 | Matt Roper | drm/i915: Add Wa_1209644611:icl,ehl Signed-off-by: Matt Roper <matthew.d.roper@intel.com> ...msgid/20200311162300.1838847-3-matthew.d.roper@intel.com |
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2020-03-13 | Matt Roper | drm/i915: Handle all MCR ranges Signed-off-by: Matt Roper <matthew.d.roper@intel.com> ...msgid/20200311162300.1838847-2-matthew.d.roper@intel.com |
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2020-03-09 | Matt Roper | drm/i915/tgl: Don't treat unslice registers as masked Signed-off-by: Matt Roper <matthew.d.roper@intel.com> ...msgid/20200306171139.1414649-1-matthew.d.roper@intel.com |
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2020-03-04 | Matt Roper | drm/i915/ehl: Check PHY type before reading DPLL frequency Signed-off-by: Matt Roper <matthew.d.roper@intel.com> ...msgid/20200303195043.959913-1-matthew.d.roper@intel.com |
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2020-03-02 | Matt Roper | drm/i915/tgl: Add Wa_22010178259:tgl Signed-off-by: Matt Roper <matthew.d.roper@intel.com> ...msgid/20200219215655.2923650-1-matthew.d.roper@intel.com ...msgid/20200228004320.127142-2-matthew.d.roper@intel.com |
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2020-03-02 | Matt Roper | drm/i915: Program MBUS with rmw during initialization Signed-off-by: Matt Roper <matthew.d.roper@intel.com> ...msgid/20200204011032.582737-1-matthew.d.roper@intel.com ...msgid/20200228004320.127142-1-matthew.d.roper@intel.com |
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2020-02-26 | Matt Roper | drm/i915/tgl: Allow DC5/DC6 entry while PG2 is active Signed-off-by: Matt Roper <matthew.d.roper@intel.com> ...msgid/20200220231843.3127468-1-matthew.d.roper@intel.com |
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2020-02-21 | Matt Roper | drm/i915/tgl: Add Wa_22010178259:tgl Signed-off-by: Matt Roper <matthew.d.roper@intel.com> ...msgid/20200219215655.2923650-1-matthew.d.roper@intel.com |
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2020-02-20 | Matt Roper | drm/i915/tgl: Program MBUS_ABOX{1,2}_CTL during display... Signed-off-by: Matt Roper <matthew.d.roper@intel.com> ...msgid/20200204011032.582737-2-matthew.d.roper@intel.com |
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2020-02-20 | Matt Roper | drm/i915: Program MBUS with rmw during initialization Signed-off-by: Matt Roper <matthew.d.roper@intel.com> ...msgid/20200204011032.582737-1-matthew.d.roper@intel.com |
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2020-02-17 | Matt Roper | drm/i915/ehl: Update port clock voltage level requirements Signed-off-by: Matt Roper <matthew.d.roper@intel.com> ...msgid/20200207001417.1229251-1-matthew.d.roper@intel.com |
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2020-02-10 | Matt Roper | drm/i915/tgl: Update cdclk voltage level settings Signed-off-by: Matt Roper <matthew.d.roper@intel.com> ...msgid/20200207001417.1229251-2-matthew.d.roper@intel.com |
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2020-02-10 | Matt Roper | drm/i915/ehl: Update port clock voltage level requirements Signed-off-by: Matt Roper <matthew.d.roper@intel.com> ...msgid/20200207001417.1229251-1-matthew.d.roper@intel.com |
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2020-01-14 | Matt Roper | drm/i915/gen11: Add additional pcode status values Signed-off-by: Matt Roper <matthew.d.roper@intel.com> ...msgid/20200111014511.2988923-1-matthew.d.roper@intel.com |
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2020-01-07 | Matt Roper | drm/i915: Add Wa_1407352427:icl,ehl Signed-off-by: Matt Roper <matthew.d.roper@intel.com> ...msgid/20191231190713.1549533-1-matthew.d.roper@intel.com |
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2020-01-07 | Matt Roper | drm/i915: Add Wa_1408615072 and Wa_1407596294 to icl,ehl Signed-off-by: Matt Roper <matthew.d.roper@intel.com> ...msgid/20191224012026.3157766-3-matthew.d.roper@intel.com |
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2020-01-01 | Matt Roper | drm/i915: Add Wa_1407352427:icl,ehl Signed-off-by: Matt Roper <matthew.d.roper@intel.com> ...msgid/20191231190713.1549533-1-matthew.d.roper@intel.com |
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2019-12-31 | Matt Roper | drm/i915/tgl: Assume future platforms will inherit... Signed-off-by: Matt Roper <matthew.d.roper@intel.com> ...msgid/20191224231521.3430660-1-matthew.d.roper@intel.com |
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2019-12-27 | Matt Roper | drm/i915/tgl: Extend Wa_1408615072 to tgl Signed-off-by: Matt Roper <matthew.d.roper@intel.com> ...msgid/20191224012026.3157766-4-matthew.d.roper@intel.com |
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2019-12-27 | Matt Roper | drm/i915: Add Wa_1408615072 and Wa_1407596294 to icl,ehl Signed-off-by: Matt Roper <matthew.d.roper@intel.com> ...msgid/20191224012026.3157766-3-matthew.d.roper@intel.com |
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2019-12-27 | Matt Roper | drm/i915: Extend WaDisableDARBFClkGating to icl,ehl,tgl Signed-off-by: Matt Roper <matthew.d.roper@intel.com> ...msgid/20191224012026.3157766-2-matthew.d.roper@intel.com |
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2019-12-16 | Matt Roper | drm/i915/tgl: Drop Wa#1178 Signed-off-by: Matt Roper <matthew.d.roper@intel.com> ...msgid/20191213001511.678070-3-matthew.d.roper@intel.com |
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2019-12-16 | Matt Roper | drm/i915/ehl: Define EHL powerwells independently of ICL Signed-off-by: Matt Roper <matthew.d.roper@intel.com> ...msgid/20191213001511.678070-2-matthew.d.roper@intel.com |
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2019-12-13 | Matt Roper | drm/i915/icl: Cleanup combo PHY aux power well handlers Signed-off-by: Matt Roper <matthew.d.roper@intel.com> ...msgid/20191213010600.701315-1-matthew.d.roper@intel.com |
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2019-12-13 | Matt Roper | drm/i915/tgl: Drop Wa#1178 Signed-off-by: Matt Roper <matthew.d.roper@intel.com> ...msgid/20191213001511.678070-3-matthew.d.roper@intel.com |
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2019-12-13 | Matt Roper | drm/i915/ehl: Define EHL powerwells independently of ICL Signed-off-by: Matt Roper <matthew.d.roper@intel.com> ...msgid/20191213001511.678070-2-matthew.d.roper@intel.com |
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2019-12-10 | Matt Roper | drm/i915/tgl: Program BW_BUDDY registers during display... Signed-off-by: Matt Roper <matthew.d.roper@intel.com> ...msgid/20191205224848.76712-1-matthew.d.roper@intel.com |
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2019-12-03 | Matt Roper | drm/i915/irq: Refactor gen11 display interrupt handling Signed-off-by: Matt Roper <matthew.d.roper@intel.com> ...msgid/20191202171608.3361125-1-matthew.d.roper@intel.com |
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2019-12-03 | Matt Roper | drm/i915/ehl: Make icp_digital_port_connected() use... Signed-off-by: Matt Roper <matthew.d.roper@intel.com> ...msgid/20191127221314.575575-2-matthew.d.roper@intel.com |
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2019-12-02 | Matt Roper | drm/i915: Program SHPD_FILTER_CNT on CNP+ Signed-off-by: Matt Roper <matthew.d.roper@intel.com> ...msgid/20191127221314.575575-3-matthew.d.roper@intel.com |
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2019-12-02 | Matt Roper | drm/i915/ehl: Make icp_digital_port_connected() use... Signed-off-by: Matt Roper <matthew.d.roper@intel.com> ...msgid/20191127221314.575575-2-matthew.d.roper@intel.com |
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2019-12-02 | Matt Roper | drm/i915: Handle SDEISR according to PCH rather than... Signed-off-by: Matt Roper <matthew.d.roper@intel.com> ...msgid/20191127221314.575575-1-matthew.d.roper@intel.com |
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2019-11-25 | Matt Roper | drm/i915/tgl: Add DKL PHY vswing table for HDMI Signed-off-by: Matt Roper <matthew.d.roper@intel.com> ...msgid/20191118180219.9309-1-matthew.d.roper@intel.com |
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2019-11-25 | Matt Roper | drm/i915/ehl: Update voltage level checks Signed-off-by: Matt Roper <matthew.d.roper@intel.com> ...msgid/20191118164412.26216-1-matthew.d.roper@intel.com |
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