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drm/i915/tgl: Add note about Wa_1409142259
2020-03-02 José Roberto de... drm/i915/tgl: Add note about Wa_1409142259
 ...off-by: José Roberto de Souza <jose.souza@intel.com>
...msgid/20200227220101.321671-8-jose.souza@intel.com
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2020-03-02 José Roberto de... drm/i915/tgl: Fix the Wa number of a fix
 ...off-by: José Roberto de Souza <jose.souza@intel.com>
...msgid/20200227220101.321671-7-jose.souza@intel.com
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2020-03-02 José Roberto de... drm/i915/tgl: Add note about Wa_1607063988
 ...off-by: José Roberto de Souza <jose.souza@intel.com>
...msgid/20200227220101.321671-6-jose.souza@intel.com
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2020-03-02 José Roberto de... drm/i915/tgl: Add note to Wa_1607297627
 ...off-by: José Roberto de Souza <jose.souza@intel.com>
...msgid/20200227220101.321671-5-jose.souza@intel.com
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2020-03-02 José Roberto de... drm/i915/tgl: Implement Wa_1806527549
 ...off-by: José Roberto de Souza <jose.souza@intel.com>
...msgid/20200227220101.321671-2-jose.souza@intel.com
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2020-03-02 José Roberto de... drm/i915/tgl: Implement Wa_1409804808
 ...off-by: José Roberto de Souza <jose.souza@intel.com>
...msgid/20200227220101.321671-1-jose.souza@intel.com
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2020-02-24 José Roberto de... drm/i915/psr: Force PSR probe only after full initialization
 ...off-by: José Roberto de Souza <jose.souza@intel.com>
...patch/msgid/20200221212635.11614-1-jose.souza@intel.com
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2020-02-15 José Roberto de... drm/i915/mst: Set intel_dp_set_m_n() for MST slaves
 ...off-by: José Roberto de Souza <jose.souza@intel.com>
...patch/msgid/20200211185008.30806-1-jose.souza@intel.com
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2020-02-12 José Roberto de... drm/i915: Fix preallocated barrier list append
 ...off-by: José Roberto de Souza <jose.souza@intel.com>
...patch/msgid/20200129232345.84512-1-jose.souza@intel.com
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2020-02-10 José Roberto de... drm/i915/dc3co: Add description of how it works
 ...off-by: José Roberto de Souza <jose.souza@intel.com>
...msgid/20200205214945.131012-1-jose.souza@intel.com
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2020-02-10 José Roberto de... drm/i915/display/ehl: Add HBR2 and HBR3 voltage swing...
...off-by: José Roberto de Souza <jose.souza@intel.com>
...patch/msgid/20200205205647.64902-1-jose.souza@intel.com
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2020-02-06 José Roberto de... drm/i915/display: Set TRANS_DDI_MODE_SELECT to default...
...off-by: José Roberto de Souza <jose.souza@intel.com>
...msgid/20200203225549.152301-1-jose.souza@intel.com
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2020-01-30 José Roberto de... drm/mst: Fix possible NULL pointer dereference in drm_dp_mst...
...off-by: José Roberto de Souza <jose.souza@intel.com>
...patch/msgid/20200129232448.84704-1-jose.souza@intel.com
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2020-01-30 José Roberto de... drm/i915: Fix preallocated barrier list append
 ...off-by: José Roberto de Souza <jose.souza@intel.com>
...patch/msgid/20200129232345.84512-1-jose.souza@intel.com
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2020-01-24 José Roberto de... drm/i915/dc3co: Avoid full modeset when EXITLINE needs...
...off-by: José Roberto de Souza <jose.souza@intel.com>
...patch/msgid/20200122182617.18597-2-jose.souza@intel.com
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2020-01-24 José Roberto de... drm/i915/dc3co: Do the full calculation of DC3CO exit...
...off-by: José Roberto de Souza <jose.souza@intel.com>
...patch/msgid/20200122182617.18597-1-jose.souza@intel.com
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2020-01-17 José Roberto de... drm/mst: Some style improvements in drm_dp_mst_topology_mgr_...
...off-by: José Roberto de Souza <jose.souza@intel.com>
...msgid/20200117015837.402239-2-jose.souza@intel.com
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2020-01-17 José Roberto de... drm/mst: Don't do atomic checks over disabled managers
 ...off-by: José Roberto de Souza <jose.souza@intel.com>
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2020-01-16 José Roberto de... drm/i915/psr: Share the computation of idle frames
 ...off-by: José Roberto de Souza <jose.souza@intel.com>
...patch/msgid/20200113214603.52158-1-jose.souza@intel.com
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2020-01-14 José Roberto de... drm/i915/vbt: Rename BDB_LVDS_POWER to BDB_LFP_POWER
 ...off-by: José Roberto de Souza <jose.souza@intel.com>
...msgid/20200110235045.176640-1-jose.souza@intel.com
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2020-01-14 José Roberto de... drm/i915/dp/tgl+: Update combo phy vswing tables
 ...off-by: José Roberto de Souza <jose.souza@intel.com>
...msgid/20200110233902.154960-1-jose.souza@intel.com
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2020-01-08 José Roberto de... drm/i915/display: Fix warning about MST and DDI restrictions
 ...off-by: José Roberto de Souza <jose.souza@intel.com>
...msgid/20200107170922.153612-2-jose.souza@intel.com
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2020-01-08 José Roberto de... drm/i915/display/icl+: Do not program clockgating
 ...off-by: José Roberto de Souza <jose.souza@intel.com>
...msgid/20200107170922.153612-1-jose.souza@intel.com
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2020-01-08 José Roberto de... drm/i915/display: Force the state compute phase once...
...off-by: José Roberto de Souza <jose.souza@intel.com>
...msgid/20200106152128.195171-1-jose.souza@intel.com
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2020-01-07 José Roberto de... drm/i915/display: Use external dependency loop for...
...off-by: José Roberto de Souza <jose.souza@intel.com>
...msgid/20200106142823.145260-1-jose.souza@intel.com
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2019-12-23 José Roberto de... drm/i915/display: Add comment to a function that probably...
...off-by: José Roberto de Souza <jose.souza@intel.com>
...patch/msgid/20191223010654.67037-7-jose.souza@intel.com
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2019-12-23 José Roberto de... drm/i915/mst: Force modeset on MST slaves when master...
...off-by: José Roberto de Souza <jose.souza@intel.com>
...patch/msgid/20191223010654.67037-6-jose.souza@intel.com
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2019-12-23 José Roberto de... drm/i915/display: Prepare for fastset external dependencies...
...off-by: José Roberto de Souza <jose.souza@intel.com>
...patch/msgid/20191223010654.67037-5-jose.souza@intel.com
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2019-12-23 José Roberto de... drm/i915/dp: Fix MST disable sequence
 ...off-by: José Roberto de Souza <jose.souza@intel.com>
...patch/msgid/20191223010654.67037-4-jose.souza@intel.com
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2019-12-23 José Roberto de... drm/i915/display: Always enables MST master pipe first
 ...off-by: José Roberto de Souza <jose.souza@intel.com>
...patch/msgid/20191223010654.67037-3-jose.souza@intel.com
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2019-12-23 José Roberto de... drm/i915/tgl: Select master transcoder for MST stream
 ...off-by: José Roberto de Souza <jose.souza@intel.com>
...patch/msgid/20191223010654.67037-2-jose.souza@intel.com
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2019-12-23 José Roberto de... drm/i915/display: Share intel_connector_needs_modeset()
 ...off-by: José Roberto de Souza <jose.souza@intel.com>
...patch/msgid/20191223010654.67037-1-jose.souza@intel.com
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2019-12-06 José Roberto de... drm/i915/display: Refactor intel_commit_modeset_disables()
 ...off-by: José Roberto de Souza <jose.souza@intel.com>
...patch/msgid/20191205210350.96795-3-jose.souza@intel.com
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2019-12-06 José Roberto de... drm/i915/display/tgl: Fix the order of the step to...
...off-by: José Roberto de Souza <jose.souza@intel.com>
...patch/msgid/20191205210350.96795-2-jose.souza@intel.com
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2019-12-06 José Roberto de... drm/i915/display: Do not check for the ddb allocations...
...off-by: José Roberto de Souza <jose.souza@intel.com>
...patch/msgid/20191205210350.96795-1-jose.souza@intel.com
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2019-12-06 José Roberto de... drm/i915: Add new EHL/JSL PCI ids
 ...off-by: José Roberto de Souza <jose.souza@intel.com>
...msgid/20191203211308.109703-1-jose.souza@intel.com
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2019-12-03 José Roberto de... drm/i915/display/mst: Move DPMS_OFF call to post_disable
 ...off-by: José Roberto de Souza <jose.souza@intel.com>
...msgid/20191202222513.337777-3-jose.souza@intel.com
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2019-12-03 José Roberto de... drm/i915/dp: Power down sink before disable pipe/transcoder...
...off-by: José Roberto de Souza <jose.souza@intel.com>
...msgid/20191202222513.337777-2-jose.souza@intel.com
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2019-12-03 José Roberto de... drm/i915/display: Check the old state to find port...
...off-by: José Roberto de Souza <jose.souza@intel.com>
...msgid/20191202222513.337777-1-jose.souza@intel.com
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2019-12-02 José Roberto de... drm/i915/display: Suspend MST topology manager before...
...off-by: José Roberto de Souza <jose.souza@intel.com>
...msgid/20191127021609.162700-1-jose.souza@intel.com
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2019-12-02 José Roberto de... drm/i915/vbt: Parse power conservation features block
 ...off-by: José Roberto de Souza <jose.souza@intel.com>
...msgid/20191128014852.214135-5-jose.souza@intel.com
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2019-12-02 José Roberto de... drm/i915/psr: Check if sink PSR capability changed
 ...off-by: José Roberto de Souza <jose.souza@intel.com>
...msgid/20191128014852.214135-4-jose.souza@intel.com
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2019-12-02 José Roberto de... drm/i915/psr: Enable ALPM lock timeout error interruption
 ...off-by: José Roberto de Souza <jose.souza@intel.com>
...msgid/20191128014852.214135-3-jose.souza@intel.com
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2019-12-02 José Roberto de... drm/i915/psr: Refactor psr short pulse handler
 ...off-by: José Roberto de Souza <jose.souza@intel.com>
...msgid/20191128014852.214135-2-jose.souza@intel.com
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2019-12-02 José Roberto de... drm/i915/psr: Add bits per pixel limitation
 ...off-by: José Roberto de Souza <jose.souza@intel.com>
...msgid/20191128014852.214135-1-jose.souza@intel.com
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2019-11-18 José Roberto de... drm/i915/mst: Check uapi enable not intel one during...
...off-by: José Roberto de Souza <jose.souza@intel.com>
...patch/msgid/20191115200430.53146-1-jose.souza@intel.com
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2019-11-18 José Roberto de... drm/i915/display: Fix TRANS_DDI_MST_TRANSPORT_SELECT...
...off-by: José Roberto de Souza <jose.souza@intel.com>
...patch/msgid/20191107214559.77087-1-jose.souza@intel.com
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2019-11-13 José Roberto de... drm/i915/display/mst: Enable virtual channel payload...
...off-by: José Roberto de Souza <jose.souza@intel.com>
...patch/msgid/20191107214559.77087-3-jose.souza@intel.com
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2019-11-13 José Roberto de... drm/i915/display/dsi: Add support to pipe D
 ...off-by: José Roberto de Souza <jose.souza@intel.com>
...patch/msgid/20191107214559.77087-2-jose.souza@intel.com
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2019-11-13 José Roberto de... drm/i915/display: Fix TRANS_DDI_MST_TRANSPORT_SELECT...
...off-by: José Roberto de Souza <jose.souza@intel.com>
...patch/msgid/20191107214559.77087-1-jose.souza@intel.com
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2019-11-04 José Roberto de... drm/i915: Add for_each_new_intel_connector_in_state()
 ...off-by: José Roberto de Souza <jose.souza@intel.com>
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2019-11-04 José Roberto de... drm/i915/dp: Do not switch aux to TBT mode for non...
...off-by: José Roberto de Souza <jose.souza@intel.com>
...msgid/20191029011014.286885-1-jose.souza@intel.com
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2019-10-31 José Roberto de... drm/i915/dp: Do not switch aux to TBT mode for non...
...off-by: José Roberto de Souza <jose.souza@intel.com>
...msgid/20191029011014.286885-1-jose.souza@intel.com
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2019-10-29 José Roberto de... drm/i915/display/cnl+: Handle fused off DSC
 ...off-by: José Roberto de Souza <jose.souza@intel.com>
...msgid/20191026001323.216052-5-jose.souza@intel.com
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2019-10-29 José Roberto de... drm/i915/display/icl+: Check if DMC is fused off
 ...off-by: José Roberto de Souza <jose.souza@intel.com>
...msgid/20191026001323.216052-4-jose.souza@intel.com
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2019-10-29 José Roberto de... drm/i915/display: Check if FBC is fused off
 ...off-by: José Roberto de Souza <jose.souza@intel.com>
...msgid/20191026001323.216052-3-jose.souza@intel.com
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2019-10-29 José Roberto de... drm/i915/display: Handle fused off HDCP
 ...off-by: José Roberto de Souza <jose.souza@intel.com>
...msgid/20191026001323.216052-2-jose.souza@intel.com
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2019-10-29 José Roberto de... drm/i915: Add two spaces before the SKL_DFSM registers
 ...off-by: José Roberto de Souza <jose.souza@intel.com>
...msgid/20191026001323.216052-1-jose.souza@intel.com
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2019-10-25 José Roberto de... drm/i915/tc: Clear DKL_TX_PMD_LANE_SUS before program...
...off-by: José Roberto de Souza <jose.souza@intel.com>
...patch/msgid/20191021223408.87344-1-jose.souza@intel.com
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2019-10-25 José Roberto de... drm/i915: Add is_dgfx to device info
 ...off-by: José Roberto de Souza <jose.souza@intel.com>
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2019-10-25 José Roberto de... drm/i915/display/psr: Print in debugfs if PSR is not...
...off-by: José Roberto de Souza <jose.souza@intel.com>
...patch/msgid/20191023214932.94679-1-jose.souza@intel.com
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2019-10-02 José Roberto de... drm/i915/mg: Use tc_port instead of port parameter...
...off-by: José Roberto de Souza <jose.souza@intel.com>
...msgid/20191001193729.123736-1-jose.souza@intel.com
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2019-09-27 José Roberto de... drm/i915/tgl: Fix dkl link training
 ...off-by: José Roberto de Souza <jose.souza@intel.com>
...patch/msgid/20190926210659.56317-3-jose.souza@intel.com
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2019-09-25 José Roberto de... drm/i915/tgl: Return the mg/dkl pll as DDI clock for...
...off-by: José Roberto de Souza <jose.souza@intel.com>
...msgid/20190924210040.142075-6-jose.souza@intel.com
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2019-09-25 José Roberto de... drm/i915/tgl: Add dkl phy pll calculations
 ...off-by: José Roberto de Souza <jose.souza@intel.com>
...msgid/20190924210040.142075-5-jose.souza@intel.com
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2019-09-23 José Roberto de... drm/i915/tgl: Check the UC health of tc controllers...
...off-by: José Roberto de Souza <jose.souza@intel.com>
...msgid/20190920205810.211048-7-jose.souza@intel.com
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2019-09-23 José Roberto de... drm/i915/icl: Unify disable and enable phy clock gating...
...off-by: José Roberto de Souza <jose.souza@intel.com>
...msgid/20190920205810.211048-6-jose.souza@intel.com
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2019-09-23 José Roberto de... drm/i915/tgl: Finish modular FIA support on registers
 ...off-by: José Roberto de Souza <jose.souza@intel.com>
...msgid/20190920205810.211048-3-jose.souza@intel.com
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2019-09-16 José Roberto de... drm/connector: Allow max possible encoders to attach...
...off-by: José Roberto de Souza <jose.souza@intel.com>
...msgid/20190913232857.389834-2-jose.souza@intel.com
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2019-09-16 José Roberto de... drm/connector: Share with non-atomic drivers the function...
...off-by: José Roberto de Souza <jose.souza@intel.com>
...msgid/20190913232857.389834-1-jose.souza@intel.com
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2019-09-05 José Roberto de... drm/i915/mst: Do not hardcoded the crtcs that encoder...
...off-by: José Roberto de Souza <jose.souza@intel.com>
...patch/msgid/20190904230241.20638-2-jose.souza@intel.com
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2019-09-05 José Roberto de... drm/i915: Apply FBC WA for TGL too
 ...off-by: José Roberto de Souza <jose.souza@intel.com>
...patch/msgid/20190904230241.20638-1-jose.souza@intel.com
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2019-09-05 José Roberto de... drm/i915/tgl: Access the right register when handling...
...off-by: José Roberto de Souza <jose.souza@intel.com>
...patch/msgid/20190904213419.27547-3-jose.souza@intel.com
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2019-09-05 José Roberto de... drm/i915/psr: Only handle interruptions of the transcoder...
...off-by: José Roberto de Souza <jose.souza@intel.com>
...patch/msgid/20190904213419.27547-2-jose.souza@intel.com
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2019-08-29 José Roberto de... drm/i915/tgl: PSR link standby is not supported anymore
 ...off-by: José Roberto de Souza <jose.souza@intel.com>
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2019-08-27 José Roberto de... drm/i915/tgl: Implement TGL DisplayPort training sequence
 ...off-by: José Roberto de Souza <jose.souza@intel.com>
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2019-08-27 José Roberto de... drm/i915: Disable pipes in reverse order
 ...off-by: José Roberto de Souza <jose.souza@intel.com>
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2019-08-27 José Roberto de... drm: Add for_each_oldnew_intel_crtc_in_state_reverse()
 ...off-by: José Roberto de Souza <jose.souza@intel.com>
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2019-08-27 José Roberto de... drm/i915/tgl: Add maximum resolution supported by PSR2 HW
 ...off-by: José Roberto de Souza <jose.souza@intel.com>
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2019-08-27 José Roberto de... drm/i915: Do not read PSR2 register in transcoders...
...off-by: José Roberto de Souza <jose.souza@intel.com>
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2019-08-27 José Roberto de... drm/i915/tgl: Guard and warn if more than one eDP panel...
...off-by: José Roberto de Souza <jose.souza@intel.com>
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2019-08-22 José Roberto de... drm/i915: Do not unmask PSR interruption in IRQ postinstall
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...patch/msgid/20190820223325.27490-3-jose.souza@intel.com
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2019-08-22 José Roberto de... drm/i915: Add transcoder restriction to PSR2
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...patch/msgid/20190820223325.27490-2-jose.souza@intel.com
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2019-08-22 José Roberto de... drm/i915/psr: Make PSR registers relative to transcoders
 ...off-by: José Roberto de Souza <jose.souza@intel.com>
...patch/msgid/20190820223325.27490-1-jose.souza@intel.com
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2019-08-20 José Roberto de... drm/i915/tgl: Move transcoders to pipes' powerwells
 ...off-by: José Roberto de Souza <jose.souza@intel.com>
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2019-08-13 José Roberto de... drm/i915: Add _TRANS2()
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...patch/msgid/20190730224753.14907-2-jose.souza@intel.com
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2019-08-13 José Roberto de... drm/i915/bdw+: Move misc display IRQ handling to it...
...off-by: José Roberto de Souza <jose.souza@intel.com>
...patch/msgid/20190730224753.14907-1-jose.souza@intel.com
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2019-08-13 José Roberto de... drm/i915/tgl: Fix missing parentheses on TGL_TRANS_DDI_FUNC_...
...off-by: José Roberto de Souza <jose.souza@intel.com>
...patch/msgid/20190812175405.14479-1-jose.souza@intel.com
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2019-08-08 José Roberto de... drm/i915/tgl: Fix the read of the DDI that transcoder...
...off-by: José Roberto de Souza <jose.souza@intel.com>
...patch/msgid/20190808004935.1787-2-jose.souza@intel.com
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2019-08-08 José Roberto de... drm/i915: Get transcoder power domain before reading...
...off-by: José Roberto de Souza <jose.souza@intel.com>
...patch/msgid/20190808004935.1787-1-jose.souza@intel.com
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2019-08-01 José Roberto de... drm/i915/tgl: Add and use new DC5 and DC6 residency...
...off-by: José Roberto de Souza <jose.souza@intel.com>
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2019-07-31 José Roberto de... drm/i915/ehl: Ungate DDIC and DDID
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...patch/msgid/20190730175121.16413-1-jose.souza@intel.com
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2019-07-30 José Roberto de... drm/i915/tgl: Update north display hotplug detection...
...off-by: José Roberto de Souza <jose.souza@intel.com>
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2019-07-15 José Roberto de... drm/i915: Enable hotplug retry
 ...off-by: José Roberto de Souza <jose.souza@intel.com>
...patch/msgid/20190712005343.24571-2-jose.souza@intel.com
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2019-07-11 José Roberto de... drm/i915/tgl: Update DPLL clock reference register
 ...off-by: José Roberto de Souza <jose.souza@intel.com>
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2019-07-11 José Roberto de... drm/i915/tgl: rename TRANSCODER_EDP_VDSC to use on...
...off-by: José Roberto de Souza <jose.souza@intel.com>
Acked-by: José Roberto de Souza <jose.souza@intel.com>
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2019-07-11 José Roberto de... drm/i915/tgl: Check if pipe D is fused
 ...off-by: José Roberto de Souza <jose.souza@intel.com>
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2019-06-26 José Roberto de... drm/i915/ehl: Add voltage level requirement table
 ...off-by: José Roberto de Souza <jose.souza@intel.com>
...patch/msgid/20190626014053.30541-3-jose.souza@intel.com
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2019-06-26 José Roberto de... drm/i915/ehl: Remove unsupported cd clocks
 ...off-by: José Roberto de Souza <jose.souza@intel.com>
...patch/msgid/20190626014053.30541-2-jose.souza@intel.com
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2019-06-26 José Roberto de... drm/i915/icl: Add new supported CD clocks
 ...off-by: José Roberto de Souza <jose.souza@intel.com>
...patch/msgid/20190626014053.30541-1-jose.souza@intel.com
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