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drm/i915: s/tc_port/hpd_pin/ in GEN11_{TC,TBT}_HOTPLUG()
2020-10-30 Ville Syrjälädrm/i915: s/tc_port/hpd_pin/ in GEN11_{TC,TBT}_HOTPLUG()
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2020-10-30 Ville Syrjälädrm/i915: s/port/hpd_pin/ for icp+ ddi hpd bits
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2020-10-30 Ville Syrjälädrm/i915: Introduce GEN8_DE_PORT_HOTPLUG()
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2020-10-30 Ville Syrjälädrm/i915: Parametrize BXT_DE_PORT_HP_DDI with hpd_pin
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2020-10-30 Ville Syrjälädrm/i915: Use AUX_CH_USBCn for the RKL VBT AUX CH setup
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2020-10-30 Ville Syrjälädrm/i915: Pimp AUX CH names
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2020-10-30 Ville Syrjälädrm/i915: Introduce AUX_CH_USBCn
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2020-10-30 Ville Syrjälädrm/i915: Give DDI encoders even better names
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2020-10-30 Ville Syrjälädrm/i915: Add PORT_TCn aliases to enum port
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2020-10-30 Ville Syrjälädrm/i915: s/PORT_TC/TC_PORT_/
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2020-10-29 Ville Syrjälädrm/i915: Use _MMIO_PIPE3() for ilk+ WM0_PIPE registers
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2020-10-21 Ville Syrjälädrm/i915: Reject 90/270 degree rotated initial fbs
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2020-10-21 Ville Syrjälädrm/i915: Clean up the irq enable/disable for ilk rps
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2020-10-21 Ville Syrjälädrm/i915: Do gen5_gt_irq_postinstall() before enabling...
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2020-10-21 Ville Syrjälädrm/i915: Fix potential overflows in ilk ips calculations
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2020-10-21 Ville Syrjälädrm/i915: Read actual GPU frequency from MEMSTAT_ILK...
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2020-10-21 Ville Syrjälädrm/i915: Restore ILK-M RPS support
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2020-10-20 Ville Syrjälädrm/i915: Sort ICL PCI IDs
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2020-10-20 Ville Syrjälädrm/i915: Sort CNL PCI IDs
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2020-10-20 Ville Syrjälädrm/i915: Sort CFL PCI IDs
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2020-10-20 Ville Syrjälädrm/i915: Sort CML PCI IDs
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2020-10-20 Ville Syrjälädrm/i915: Sort KBL PCI IDs
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2020-10-20 Ville Syrjälädrm/i915: Sort SKL PCI IDs
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2020-10-20 Ville Syrjälädrm/i915: Sort HSW PCI IDs
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2020-10-20 Ville Syrjälädrm/i915: Ocd the HSW PCI ID hex numbers
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2020-10-20 Ville Syrjälädrm/i915: Try to fix the SKL GT3/4 vs. GT3e/4e comments
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2020-10-20 Ville Syrjälädrm/i915: Sort the mess around ICP TC hotplugs regs
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2020-10-20 Ville Syrjälädrm/i915: Refactor .hpd_irq_setup() calls a bit
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2020-10-20 Ville Syrjälädrm/i915: Reorder hpd init vs. display resume
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2020-10-20 Ville Syrjälädrm/i915: s/intel_dp_sink_dpms/intel_dp_set_power/
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2020-10-20 Ville Syrjälädrm/i915: Move the lspcon resume from .reset() to intel_dp_s...
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2020-10-16 Ville Syrjälädrm/i915: Inline intel_dp_ycbcr420_config()
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2020-10-16 Ville Syrjälädrm/i915: Nuke lspcon_ycbcr420_config()
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2020-10-16 Ville Syrjälädrm/i915: Nuke lspcon_downsampling
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2020-10-16 Ville Syrjälädrm/i915: Mark initial fb obj as WT on eLLC machines...
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2020-10-16 Ville Syrjälädrm/i915: Apply WAC6entrylatency to kbl/cfl
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2020-10-09 Ville Syrjälädrm/i915: s/int/u32/ for aux_offset/alignment
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2020-10-09 Ville Syrjälädrm/i915: Skip aux plane stuff when there is no aux...
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2020-10-09 Ville Syrjälädrm/i915: Set all unused color plane offsets to ~0xfff...
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2020-10-09 Ville Syrjälädrm/i915: Rename i915_{save,restore}_state()
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2020-10-09 Ville Syrjälädrm/i915: Wait for VLV/CHV/BXT/GLK DSI panel power...
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2020-10-09 Ville Syrjälädrm/i915: Wait for LVDS panel power cycle delay on...
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2020-10-09 Ville Syrjälädrm/i915: Wait for eDP panel power cycle delay on reboot...
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2020-10-09 Ville Syrjälädrm/i915: Replace the VLV/CHV eDP reboot notifier with...
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2020-10-09 Ville Syrjälädrm/i915: Add an encoder .shutdown() hook
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2020-10-09 Ville Syrjälädrm/i915: Shut down displays gracefully on reboot
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2020-10-02 Ville Syrjälädrm/i915: Make lspcon_init() static
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2020-10-01 Ville Syrjälädrm/i915: Eliminate intel_dp.regs.dp_tp_{ctl,status}
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2020-10-01 Ville Syrjälädrm/i915: Plumb crtc_state to link training
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2020-10-01 Ville Syrjälädrm/i915: Split TGL DKL PHY buf trans per output type
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2020-10-01 Ville Syrjälädrm/i915: Split TGL combo PHY buf trans per output...
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2020-10-01 Ville Syrjälädrm/i915: Split EHL combo PHY buf trans per output...
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2020-10-01 Ville Syrjälädrm/i915: Split ICL MG PHY buf trans per output type
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2020-10-01 Ville Syrjälädrm/i915: Split ICL combo PHY buf trans per output...
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2020-10-01 Ville Syrjälädrm/i915: Shove the PHY test into the hotplug work
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2020-10-01 Ville Syrjälädrm/i915: Make intel_dp_process_phy_request() static
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2020-10-01 Ville Syrjälädrm/i915: s/old_crtc_state/crtc_state/
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2020-10-01 Ville Syrjälädrm/i915: s/pre_empemph/preemph/
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2020-10-01 Ville Syrjälädrm/i915: Fix TGL DKL PHY DP vswing handling
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2020-09-30 Ville Syrjälädrm/i915: Implement display WA #1142:kbl,cfl,cml
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2020-09-30 Ville Syrjälädrm/i915: Read DIMM size in Gb rather than GB
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2020-09-28 Ville Syrjälädrm/i915: Replace some gamma_mode ifs with switches
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2020-09-28 Ville Syrjälädrm/i915: Polish bdw_read_lut_10() a bit
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2020-09-28 Ville Syrjälädrm/i915: Relocate CHV CGM gamma masks
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2020-09-28 Ville Syrjälädrm/i915: Shuffle chv_cgm_gamma_pack() around a bit
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2020-09-28 Ville Syrjälädrm/i915: Reset glk degamma index after programming...
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2020-09-28 Ville Syrjälädrm/i915: s/glk_read_lut_10/bdw_read_lut_10/
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2020-09-28 Ville Syrjälädrm/i915: Include the LUT sizes in the state dump
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2020-09-28 Ville Syrjälädrm/i915: Move MST master transcoder dump earlier
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2020-09-28 Ville Syrjälädrm/i915: Fix state checker hw.active/hw.enable readout
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2020-09-28 Ville Syrjälädrm/i915: Don't hide the intel_crtc_atomic_check()...
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2020-09-28 Ville Syrjälädrm/i915: Make intel_{enable,disable}_sagv() static
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2020-09-24 Ville Syrjälädrm/i915: Use the correct bpp when validating "4:2...
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2020-09-24 Ville Syrjälädrm/i915: Decouple intel_dp_{min,output}_bpp() from...
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2020-09-24 Ville Syrjälädrm/i915: Extract intel_dp_output_format()
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2020-09-17 Ville Syrjälädrm/i915: Nuke force_min_cdclk_changed
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2020-09-17 Ville Syrjälädrm/i915: Remove the old global state stuff
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2020-09-17 Ville Syrjälädrm/i915: Do YCbCr 444->420 conversion via DP protocol...
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2020-09-17 Ville Syrjälädrm/dp: Add helpers for DFP YCbCr 4:2:0 handling
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2020-09-17 Ville Syrjälädrm/i915: DP->HDMI TMDS clock limits vs. deep color
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2020-09-17 Ville Syrjälädrm/i915: Extract intel_hdmi_has_audio()
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2020-09-17 Ville Syrjälädrm/i915: Handle downstream facing ports w/o EDID
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2020-09-17 Ville Syrjälädrm/dp: Add drm_dp_downstream_mode()
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2020-09-17 Ville Syrjälädrm/i915: Configure DP 1.3+ protocol converted HDMI...
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2020-09-17 Ville Syrjälädrm/i915: Deal with TMDS DFP clock limits
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2020-09-17 Ville Syrjälädrm/dp: Add drm_dp_downstream_{min,max}_tmds_clock()
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2020-09-17 Ville Syrjälädrm/i915: Reworkd DP DFP clock handling
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2020-09-17 Ville Syrjälädrm/dp: Redo drm_dp_downstream_max_clock() as drm_dp_downstr...
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2020-09-17 Ville Syrjälädrm/dp: Pimp drm_dp_downstream_max_bpc()
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2020-09-17 Ville Syrjälädrm/dp: Add helpers to identify downstream facing port...
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2020-09-17 Ville Syrjälädrm/i915: Reworkd DFP max bpc handling
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2020-09-17 Ville Syrjälädrm/dp: Define more downstream facing port caps
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2020-09-17 Ville Syrjälädrm/dp: Define protocol converter DPCD registers
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2020-09-17 Ville Syrjälädrm/i915/lspcon: Do not send infoframes to non-HDMI...
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2020-09-17 Ville Syrjälädrm/dp: Dump downstream facing port caps
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2020-09-15 Ville Syrjälädrm/i915: Nuke pointless variable
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2020-09-15 Ville Syrjälädrm/i915: Introduce intel_hpd_hotplug_irqs()
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2020-09-15 Ville Syrjälädrm/i915: Introduce HPD_PORT_TC<n>
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2020-09-15 Ville Syrjälädrm/i915: Move hpd_pin setup to encoder init
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2020-09-15 Ville Syrjälädrm/i915: Split icp_hpd_detection_setup() into ddi...
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