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drm/i915/icl: avoid unclaimed PLANE_NV12_BUF_CFG register
2018-08-02 Paulo Zanonidrm/i915/icl: avoid unclaimed PLANE_NV12_BUF_CFG register
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
...msgid/20180801004614.22149-1-paulo.r.zanoni@intel.com
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2018-07-27 Anusha Srivatsadrm/i915/icl: Set TBT IO in Aux transaction
Cc: Paulo Zanoni <paulo.r.zanoni@intel.com>
Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
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2018-07-27 Anusha Srivatsadrm/i915/icl: Add TBT checks for PLL calculations
Cc: Paulo Zanoni <paulo.r.zanoni@intel.com>
Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
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2018-07-27 Paulo Zanonidrm/i915: inline skl_copy_ddb_for_pipe() to its only...
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
...msgid/20180607230700.28359-1-paulo.r.zanoni@intel.com
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2018-07-27 Paulo Zanonidrm/i915/icl: don't set CNL_DDI_CLOCK_REG_ACCESS_ON...
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
...msgid/20180726001229.13791-1-paulo.r.zanoni@intel.com
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2018-07-25 Paulo Zanonidrm/i915/icl: toggle PHY clock gating around link training
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
...msgid/20180725002813.6938-6-paulo.r.zanoni@intel.com
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2018-07-25 Paulo Zanonidrm/i915/icl: program MG_DP_MODE
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
...msgid/20180725002813.6938-5-paulo.r.zanoni@intel.com
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2018-07-25 Animesh Mannadrm/i915/icl: Update FIA supported lane count for hpd.
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
...msgid/20180725002813.6938-4-paulo.r.zanoni@intel.com
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2018-07-25 Paulo Zanonidrm/i915/icl: store the port type for TC ports
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
...msgid/20180725002813.6938-3-paulo.r.zanoni@intel.com
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2018-07-25 Paulo Zanonidrm/i915/icl: implement icl_digital_port_connected()
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
...msgid/20180725195927.12059-1-paulo.r.zanoni@intel.com
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2018-07-24 Manasi Navaredrm/i915/icl: Implement voltage swing programming sequence...
Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
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2018-07-24 Manasi Navaredrm/i915/icl: Add remaining registers and bitfields...
Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
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2018-07-19 Paulo Zanonidrm/i915/icl: compute the TBT PLL registers
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
...msgid/20180711215909.23945-2-paulo.r.zanoni@intel.com
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2018-06-27 Anusha Srivatsadrm/i915/icp: Add Interrupt Support
Cc: Paulo Zanoni <paulo.r.zanoni@intel.com>
Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
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2018-06-20 Radhakrishna Sripadadrm/i915/icl: Add 10-bit support for hdmi
Cc: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
...msgid/20180522002558.29262-18-paulo.r.zanoni@intel.com
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2018-06-18 Dhinakaran Pandiyandrm/i915/icl: Handle hotplug interrupts for DP over TBT
Cc: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
...msgid/20180616000530.5357-3-paulo.r.zanoni@intel.com
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2018-06-18 Dhinakaran Pandiyandrm/i915/icl: Support for TC North Display interrupts
Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
...msgid/20180616000530.5357-2-paulo.r.zanoni@intel.com
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2018-06-18 Dhinakaran Pandiyandrm/i915/icl: GSE interrupt moves from DE_MISC to GU_MISC
Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
...msgid/20180616000530.5357-1-paulo.r.zanoni@intel.com
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2018-06-18 Paulo Zanonidrm/i915/i915_reg.h: fix the checkpatch MACRO_ARG_PRECEDENCE...
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
...msgid/20180612235654.7914-4-paulo.r.zanoni@intel.com
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2018-06-18 Paulo Zanonidrm/i915/i915_reg.h: fix the checkpatch SPACE_BEFORE_TAB...
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
...msgid/20180612235654.7914-3-paulo.r.zanoni@intel.com
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2018-06-18 Paulo Zanonidrm/i915/i915_reg.h: fix the checkpatch SPACING issues
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
...patch/msgid/20180618180943.894-1-paulo.r.zanoni@intel.com
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2018-06-15 Paulo Zanonidrm/i915/icl: update VBT's child_device_config flags2...
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
...msgid/20180614221018.19044-2-paulo.r.zanoni@intel.com
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2018-06-15 Paulo Zanonidrm/i915/icl: implement DVFS for ICL
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
...msgid/20180614221018.19044-1-paulo.r.zanoni@intel.com
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2018-06-14 Manasi Navaredrm/i915/dp: Add support for HBR3 and TPS4 during link...
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
...msgid/20180611222655.5696-2-paulo.r.zanoni@intel.com
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2018-06-14 Manasi Navaredrm/i915/icl: Add allowed DP rates for Icelake
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
...msgid/20180611222655.5696-1-paulo.r.zanoni@intel.com
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2018-06-14 Paulo Zanonidrm/i915/icl: start adding the TBT pll
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
...msgid/20180522002558.29262-15-paulo.r.zanoni@intel.com
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2018-06-14 Paulo Zanonidrm/i915/icl: unconditionally init DDI for every port
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
...msgid/20180522002558.29262-14-paulo.r.zanoni@intel.com
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2018-06-14 Paulo Zanonidrm/i915/icl: add icelake_get_ddi_pll()
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
...msgid/20180522002558.29262-11-paulo.r.zanoni@intel.com
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2018-06-12 James Ausmusdrm/i915/icl: DP_AUX_E is valid on ICL+
Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
...msgid/20180612002512.29783-2-paulo.r.zanoni@intel.com
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2018-06-12 Mahesh Kumardrm/i915/icl: fix gmbus gpio pin mapping
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
...msgid/20180612002512.29783-1-paulo.r.zanoni@intel.com
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2018-06-12 Manasi Navaredrm/i915/icl: Add DDI HDMI level selection for ICL
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
...msgid/20180522002558.29262-8-paulo.r.zanoni@intel.com
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2018-06-04 Mahesh Kumardrm/i915/icl: Don't update enabled dbuf slices struct...
Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
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2018-06-01 Arkadiusz Hilerdrm/i915/icl: Calculate link clock using the new registers
Cc: Paulo Zanoni <paulo.r.zanoni@intel.com>
Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
...msgid/20180522002558.29262-13-paulo.r.zanoni@intel.com
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2018-06-01 Manasi Navaredrm/i915/icl: Get DDI clock for ICL based on PLLs.
Cc: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
...msgid/20180523224444.19017-1-paulo.r.zanoni@intel.com
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2018-06-01 Anusha Srivatsadrm/i915/icl: Add Icelake PCH detection
Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Suggested-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
...msgid/20180522002558.29262-10-paulo.r.zanoni@intel.com
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2018-06-01 Radhakrishna Sripadadrm/i915/icl: Map VBT DDC Pin to BSpec DDC Pin
Cc: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
...msgid/20180522002558.29262-9-paulo.r.zanoni@intel.com
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2018-06-01 Manasi Navaredrm/i915/icl: Add register definition for DFLEXDPMLE
Cc: Paulo Zanoni <paulo.r.zanoni@intel.com>
Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
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2018-06-01 Paulo Zanonidrm/i915/icl: introduce tc_port
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
...msgid/20180522002558.29262-4-paulo.r.zanoni@intel.com
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2018-06-01 Dhinakaran Pandiyandrm/i915/icl: Extend AUX F interrupts to ICL
Cc: Paulo Zanoni <paulo.r.zanoni@intel.com>
Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
...msgid/20180522002558.29262-2-paulo.r.zanoni@intel.com
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2018-06-01 Mahesh Kumardrm/i915/icl: fix icl_unmap/map_plls_to_ports
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
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2018-05-23 José Roberto de... drm/i915/icl: Disable pipe CSC and gamma in cursor...
Cc: Paulo Zanoni <paulo.r.zanoni@intel.com>
Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
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2018-05-17 Paulo Zanonidrm/i915: enable the pipe/transcoder/planes later on...
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
...msgid/20180502215851.30736-1-paulo.r.zanoni@intel.com
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2018-05-17 Oscar Mateodrm/i915/icl: Read the correct Gen11 interrupt registers
Suggested-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
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2018-05-07 Paulo Zanonidrm/i915/icl: compute the MG PLL registers
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
...msgid/20180328215803.13835-7-paulo.r.zanoni@intel.com
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2018-05-07 Paulo Zanonidrm/i915/icl: compute the combo PHY (DPLL) DP registers
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
...msgid/20180328215803.13835-6-paulo.r.zanoni@intel.com
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2018-05-07 Paulo Zanonidrm/i915/icl: compute the combo PHY (DPLL) HDMI registers
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
...msgid/20180328215803.13835-5-paulo.r.zanoni@intel.com
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2018-05-07 Paulo Zanonidrm/i915/icl: add basic support for the ICL clocks
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
...msgid/20180427231436.9353-1-paulo.r.zanoni@intel.com
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2018-05-03 Tomasz Lisdrm/i915/icl: Add configuring MOCS in new Icelake engines
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
...msgid/20180502223142.3891-1-paulo.r.zanoni@intel.com
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2018-04-30 Manasi Navaredrm/i915/icl: Fix the DP Max Voltage for ICL
Cc: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
...msgid/20180328215803.13835-9-paulo.r.zanoni@intel.com
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2018-04-30 Manasi Navaredrm/i915/icl: Implement voltage swing programming sequence...
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
...msgid/20180328215803.13835-8-paulo.r.zanoni@intel.com
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2018-04-28 Paulo Zanonidrm/i915/icl: add definitions for the ICL PLL registers
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
...msgid/20180328215803.13835-3-paulo.r.zanoni@intel.com
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2018-04-27 James Ausmusdrm/i915/icl: Don't set pipe CSC/Gamma in PLANE_COLOR_CTL
Cc: Paulo Zanoni <paulo.r.zanoni@intel.com>
Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
...msgid/20180328215803.13835-2-paulo.r.zanoni@intel.com
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2018-03-28 Paulo Zanonidrm/i915/gen11: add support for reading the timestamp...
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
...msgid/20180109232835.11478-18-paulo.r.zanoni@intel.com
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2018-03-23 Paulo Zanonidrm/i915: protect macro parameters in SWING_SEL_{UPP...
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
...msgid/20180323195853.4599-1-paulo.r.zanoni@intel.com
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2018-03-23 Nabendu Maitidrm/i915/icl: Added 5k source scaling support for Gen11...
Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
...msgid/20180323172419.24911-7-paulo.r.zanoni@intel.com
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2018-03-23 Dhinakaran Pandiyandrm/i915/icl: HPD pin for port F
Cc: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
...msgid/20180323172419.24911-6-paulo.r.zanoni@intel.com
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2018-03-23 Manasi Navaredrm/i915/icl: Add Voltage swing table for MG PHY DDI...
Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
...msgid/20180323172419.24911-5-paulo.r.zanoni@intel.com
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2018-03-23 Manasi Navaredrm/i915/icl: Add register defs for voltage swing sequences...
Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
...msgid/20180323172419.24911-4-paulo.r.zanoni@intel.com
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2018-03-23 Manasi Navaredrm/i915/icl: Add Combo PHY DDI Buffer translation...
Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
...msgid/20180323172419.24911-3-paulo.r.zanoni@intel.com
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2018-03-23 Manasi Navaredrm/i915/icl: Add register definitions for Combo PHY...
Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
...msgid/20180323172419.24911-2-paulo.r.zanoni@intel.com
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2018-02-13 Mahesh Kumardrm/i915/icl: program mbus during pipe enable
Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
...msgid/20180205172131.20255-1-paulo.r.zanoni@intel.com
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2018-02-13 Mahesh Kumardrm/i915/icl: initialize MBus during display init
Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
...msgid/20180205154046.11485-6-paulo.r.zanoni@intel.com
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2018-02-13 Mahesh Kumardrm/i915/icl: Enable both DBuf slices during init
Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
...msgid/20180205154046.11485-5-paulo.r.zanoni@intel.com
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2018-02-13 Paulo Zanonidrm/i915/icl: implement the display init/uninit sequences
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
...msgid/20180205154046.11485-4-paulo.r.zanoni@intel.com
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2018-02-13 Paulo Zanonidrm/i915/icl: add the main CDCLK functions
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
...msgid/20180206193346.18272-1-paulo.r.zanoni@intel.com
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2018-02-13 Paulo Zanonidrm/i915/icl: add ICL support to cnl_set_procmon_ref_values
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
...msgid/20180205154046.11485-2-paulo.r.zanoni@intel.com
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2018-01-31 Paulo Zanonidrm/i915/icl: allow the reg_read ioctl to read the...
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
...msgid/20180130134918.32283-10-paulo.r.zanoni@intel.com
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2018-01-31 Kelvin Gardinerdrm/i915/icl: Set graphics mode register for gen11
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
...msgid/20180130134918.32283-9-paulo.r.zanoni@intel.com
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2018-01-31 James Ausmusdrm/i915/icl: Handle expanded PLANE_CTL_FORMAT field
Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
...msgid/20180130134918.32283-8-paulo.r.zanoni@intel.com
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2018-01-31 Paulo Zanonidrm/i915/gen11: fix the SAGV block time for gen11
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
...msgid/20180130134918.32283-7-paulo.r.zanoni@intel.com
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2018-01-31 Mahesh Kumardrm/i915/icl: Introduce MBus related registers
Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
...msgid/20180130134918.32283-6-paulo.r.zanoni@intel.com
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2018-01-31 Mahesh Kumardrm/i915/icl: NV12 y-plane ddb is not in same plane
Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
...msgid/20180130134918.32283-5-paulo.r.zanoni@intel.com
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2018-01-31 Mahesh Kumardrm/i915/icl: Fail flip if ddb allocated are less than...
Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
...msgid/20180130134918.32283-4-paulo.r.zanoni@intel.com
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2018-01-31 Mahesh Kumardrm/i915/icl: Do not fix dbuf block size to 512
Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
...msgid/20180130134918.32283-3-paulo.r.zanoni@intel.com
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2018-01-31 Mahesh Kumardrm/i915/icl: Don't allocate fixed bypass path blocks...
Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
...msgid/20180130134918.32283-2-paulo.r.zanoni@intel.com
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2018-01-19 Tvrtko Ursulindrm/i915/icl: Gen11 render context size
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
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2018-01-19 Oscar Mateodrm/i915: Return a default RCS context size
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
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2018-01-19 Tvrtko Ursulindrm/i915/icl: Icelake interrupt register addresses...
Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
...msgid/20180109232336.11029-5-paulo.r.zanoni@intel.com
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2018-01-19 Anusha Srivatsadrm/i915/icp: Add the ID for ICL PCH - ICP
Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
...msgid/20180111180010.24357-9-paulo.r.zanoni@intel.com
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2018-01-19 Anusha Srivatsadrm/i915/icp: add ICP gmbus and gpio support
Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
...msgid/20180111180010.24357-8-paulo.r.zanoni@intel.com
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2018-01-19 Anusha Srivatsadrm/i915/icp: Add backlight Support for ICP
Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
...msgid/20180119184812.2888-1-paulo.r.zanoni@intel.com
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
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2018-01-19 Anusha Srivatsadrm/i915/icp: Add Panel Power Sequencing Support
Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
...msgid/20180111180010.24357-6-paulo.r.zanoni@intel.com
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2018-01-19 Anusha Srivatsadrm/i915/icp: Get/set proper Raw clock frequency on ICP
Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
...msgid/20180111180010.24357-5-paulo.r.zanoni@intel.com
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2018-01-19 Anusha Srivatsadrm/i915/icp: Introduce Ice Lake PCH
Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
...msgid/20180111180010.24357-4-paulo.r.zanoni@intel.com
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2018-01-19 Rodrigo Vividrm/i915/icl: Add initial Icelake definitions.
Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
...msgid/20180111180010.24357-3-paulo.r.zanoni@intel.com
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2018-01-19 Rodrigo Vividrm/i915/cnl: Add Port F definition.
Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
...msgid/20180111180010.24357-2-paulo.r.zanoni@intel.com
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2017-12-04 Lionel Landwerlindrm/i915/cnl: only divide up base frequency with crystal...
Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
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2017-10-09 Paulo Zanonidrm/i915: avoid division by zero on cnl_calc_wrpll_link
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
...msgid/20171005213842.11423-2-paulo.r.zanoni@intel.com
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2017-10-09 Paulo Zanonidrm/i915: add the BXT and CNL DPLL registers to pipe_config_...
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
...msgid/20170922205343.16006-2-paulo.r.zanoni@intel.com
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2017-08-26 Praveen Paneridrm/i915: Fix FBC cfb stride programming for non X...
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
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2017-08-26 Paulo Zanonidrm/i915/cnl: don't hardcode DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
...msgid/20170825194004.26571-1-paulo.r.zanoni@intel.com
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2017-08-17 Anusha Srivatsadrm/i915: Split pin mapping into per platform functions
Cc: Paulo Zanoni <paulo.r.zanoni@intel.com>
Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
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2017-03-31 Paulo Zanonidrm/i915: make a few DDI functions static
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
...1490907472-10883-1-git-send-email-paulo.r.zanoni@intel.com
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2017-03-27 Paulo Zanonidrm/i915: kill intel_ddi_pll_select()
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
...1490209125-20046-2-git-send-email-paulo.r.zanoni@intel.com
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2017-03-22 Paulo Zanonidrm/i915: simplify intel_ddi_pll_select()
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
...1490209125-20046-1-git-send-email-paulo.r.zanoni@intel.com
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2017-03-22 Pandiyan, Dhinakarandrm/i915: Implement cdclk restrictions based on Azalia...
Cc: Paulo Zanoni <paulo.r.zanoni@intel.com>
Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
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2017-03-22 Pandiyan, Dhinakarandrm/i915/glk: Apply cdclk workaround for DP audio
Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
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2017-03-07 Paulo Zanonidrm/i915: move the {skl, bxt}_{i, uni}nit_cdclk declarations
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
...1487712207-17181-1-git-send-email-paulo.r.zanoni@intel.com
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2017-03-07 Paulo Zanonidrm/i915: remove potentially confusing IS_G4X checks
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
...1487620842-22893-3-git-send-email-paulo.r.zanoni@intel.com
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2017-01-27 Paulo Zanonidrm/i915: make i915_stolen_to_physical() return phys_addr_t
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
...1485461947-16030-1-git-send-email-paulo.r.zanoni@intel.com
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