From a47cc3ab051f963ebca820dc48e887e9a7101244 Mon Sep 17 00:00:00 2001 From: Taimur Hassan Date: Sun, 4 Oct 2020 15:20:45 -0400 Subject: [PATCH] drm/amd/display: Raise DPG height during timing synchronization [Why] Underflow counter increases in AGM when performing some mode switches due to timing sync, which is a known hardware issue. [How] Temporarily raise DPG height during timing sync so that underflow is not reported. Signed-off-by: Taimur Hassan Acked-by: Aurabindo Pillai Signed-off-by: Alex Deucher --- .../amd/display/dc/dcn10/dcn10_hw_sequencer.c | 20 ++++++++++++++++++- .../gpu/drm/amd/display/dc/dcn10/dcn10_opp.c | 1 + .../gpu/drm/amd/display/dc/dcn20/dcn20_opp.c | 12 +++++++++++ .../gpu/drm/amd/display/dc/dcn20/dcn20_opp.h | 4 ++++ drivers/gpu/drm/amd/display/dc/inc/hw/opp.h | 5 +++++ 5 files changed, 41 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c index 9528e3a46b28..6b141c9f521f 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c @@ -1847,10 +1847,20 @@ void dcn10_enable_timing_synchronization( struct pipe_ctx *grouped_pipes[]) { struct dc_context *dc_ctx = dc->ctx; - int i; + struct output_pixel_processor *opp; + struct timing_generator *tg; + int i, width, height; DC_SYNC_INFO("Setting up OTG reset trigger\n"); + for (i = 1; i < group_size; i++) { + opp = grouped_pipes[i]->stream_res.opp; + tg = grouped_pipes[i]->stream_res.tg; + tg->funcs->get_otg_active_size(tg, &width, &height); + if (opp->funcs->opp_program_dpg_dimensions) + opp->funcs->opp_program_dpg_dimensions(opp, width, 2*(height) + 1); + } + for (i = 1; i < group_size; i++) grouped_pipes[i]->stream_res.tg->funcs->enable_reset_trigger( grouped_pipes[i]->stream_res.tg, @@ -1867,6 +1877,14 @@ void dcn10_enable_timing_synchronization( grouped_pipes[i]->stream_res.tg->funcs->disable_reset_trigger( grouped_pipes[i]->stream_res.tg); + for (i = 1; i < group_size; i++) { + opp = grouped_pipes[i]->stream_res.opp; + tg = grouped_pipes[i]->stream_res.tg; + tg->funcs->get_otg_active_size(tg, &width, &height); + if (opp->funcs->opp_program_dpg_dimensions) + opp->funcs->opp_program_dpg_dimensions(opp, width, height); + } + DC_SYNC_INFO("Sync complete\n"); } diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.c index d79718fde5a6..d54d731415d7 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.c +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.c @@ -403,6 +403,7 @@ static const struct opp_funcs dcn10_opp_funcs = { .opp_program_stereo = opp1_program_stereo, .opp_pipe_clock_control = opp1_pipe_clock_control, .opp_set_disp_pattern_generator = NULL, + .opp_program_dpg_dimensions = NULL, .dpg_is_blanked = NULL, .opp_destroy = opp1_destroy }; diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_opp.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_opp.c index 138321e151eb..0784d0198661 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_opp.c +++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_opp.c @@ -290,6 +290,17 @@ void opp2_set_disp_pattern_generator( } } +void opp2_program_dpg_dimensions( + struct output_pixel_processor *opp, + int width, int height) +{ + struct dcn20_opp *oppn20 = TO_DCN20_OPP(opp); + + REG_SET_2(DPG_DIMENSIONS, 0, + DPG_ACTIVE_WIDTH, width, + DPG_ACTIVE_HEIGHT, height); +} + void opp2_dpg_set_blank_color( struct output_pixel_processor *opp, const struct tg_color *color) @@ -350,6 +361,7 @@ static struct opp_funcs dcn20_opp_funcs = { .opp_program_stereo = opp1_program_stereo, .opp_pipe_clock_control = opp1_pipe_clock_control, .opp_set_disp_pattern_generator = opp2_set_disp_pattern_generator, + .opp_program_dpg_dimensions = opp2_program_dpg_dimensions, .dpg_is_blanked = opp2_dpg_is_blanked, .opp_dpg_set_blank_color = opp2_dpg_set_blank_color, .opp_destroy = opp1_destroy, diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_opp.h b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_opp.h index 64c5b429c79a..3ab221bdd27d 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_opp.h +++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_opp.h @@ -153,6 +153,10 @@ void opp2_set_disp_pattern_generator( int height, int offset); +void opp2_program_dpg_dimensions( + struct output_pixel_processor *opp, + int width, int height); + bool opp2_dpg_is_blanked(struct output_pixel_processor *opp); void opp2_dpg_set_blank_color( diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/opp.h b/drivers/gpu/drm/amd/display/dc/inc/hw/opp.h index 2717352eb697..7617fabbd16e 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/hw/opp.h +++ b/drivers/gpu/drm/amd/display/dc/inc/hw/opp.h @@ -313,6 +313,11 @@ struct opp_funcs { int height, int offset); + void (*opp_program_dpg_dimensions)( + struct output_pixel_processor *opp, + int width, + int height); + bool (*dpg_is_blanked)( struct output_pixel_processor *opp); -- 2.20.1