From a21906ead6a59419613f803460ca900f2560b1e1 Mon Sep 17 00:00:00 2001 From: =?utf8?q?Jos=C3=A9=20Roberto=20de=20Souza?= Date: Mon, 19 Oct 2020 10:56:09 -0700 Subject: [PATCH] drm/i915/display/fbc: Implement WA 22010751166 MIME-Version: 1.0 Content-Type: text/plain; charset=utf8 Content-Transfer-Encoding: 8bit Underruns happens when plane height + y offset is not a modulo of 4 when FBC is enabled. It happens when scanline is at vactive - 10 but that is not feasible to do from the software side so here completely disabling FBC when height + y offset matches to avoid visual glitches. Specification says that it only affects TGL display C stepping and newer but to simply the check and as TGL is already in final costumers hands, pre-production display stepping A and B was also included. BSpec: 52887 ICL BSpec: 52888 EHL/JSL BSpec: 52890/55378 TGL BSpec: 53508 DG1 BSpec: 53273 RKL Signed-off-by: José Roberto de Souza Reviewed-by: Matt Roper Link: https://patchwork.freedesktop.org/patch/msgid/20201019175609.28715-1-jose.souza@intel.com --- drivers/gpu/drm/i915/display/intel_fbc.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c b/drivers/gpu/drm/i915/display/intel_fbc.c index 135f5e8a4d70..a5b072816a7b 100644 --- a/drivers/gpu/drm/i915/display/intel_fbc.c +++ b/drivers/gpu/drm/i915/display/intel_fbc.c @@ -907,6 +907,13 @@ static bool intel_fbc_can_activate(struct intel_crtc *crtc) return false; } + /* Wa_22010751166: icl, ehl, tgl, dg1, rkl */ + if (INTEL_GEN(dev_priv) >= 11 && + (cache->plane.src_h + cache->plane.adjusted_y) % 4) { + fbc->no_fbc_reason = "plane height + offset is non-modulo of 4"; + return false; + } + return true; } -- 2.20.1