From 9fc64eade85dbb1e92944ad07b14c4c24d8c08dc Mon Sep 17 00:00:00 2001 From: Qingqing Zhuo Date: Thu, 3 Aug 2023 00:55:47 -0400 Subject: [PATCH] drm/amd/display: Update DCN20 for DCN35 support [Why & How] Update DCN20 files for DCN35 usage. Signed-off-by: Qingqing Zhuo Acked-by: Harry Wentland Signed-off-by: Alex Deucher --- .../gpu/drm/amd/display/dc/dcn20/dcn20_dccg.h | 64 +++++++++++++++++++ .../drm/amd/display/dc/dcn20/dcn20_hwseq.c | 8 ++- .../drm/amd/display/dc/dcn20/dcn20_hwseq.h | 5 ++ .../amd/display/dc/inc/hw_sequencer_private.h | 2 + 4 files changed, 77 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dccg.h b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dccg.h index c8602bcfa393..ab6d09c6fe34 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dccg.h +++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dccg.h @@ -240,12 +240,66 @@ type DTBCLK_P3_EN;\ type DENTIST_DISPCLK_CHG_DONE; +#define DCCG35_REG_FIELD_LIST(type) \ + type DPPCLK0_EN;\ + type DPPCLK1_EN;\ + type DPPCLK2_EN;\ + type DPPCLK3_EN;\ + type DSCCLK0_EN;\ + type DSCCLK1_EN;\ + type DSCCLK2_EN;\ + type DSCCLK3_EN;\ + type DISPCLK_DCCG_GATE_DISABLE;\ + type DCCG_GLOBAL_FGCG_REP_DIS; \ + type PHYASYMCLK_EN;\ + type PHYASYMCLK_SRC_SEL;\ + type PHYBSYMCLK_EN;\ + type PHYBSYMCLK_SRC_SEL;\ + type PHYCSYMCLK_EN;\ + type PHYCSYMCLK_SRC_SEL;\ + type PHYDSYMCLK_EN;\ + type PHYDSYMCLK_SRC_SEL;\ + type PHYESYMCLK_EN;\ + type PHYESYMCLK_SRC_SEL;\ + type PHYASYMCLK_ROOT_GATE_DISABLE;\ + type PHYBSYMCLK_ROOT_GATE_DISABLE;\ + type PHYCSYMCLK_ROOT_GATE_DISABLE;\ + type PHYDSYMCLK_ROOT_GATE_DISABLE;\ + type PHYESYMCLK_ROOT_GATE_DISABLE;\ + type HDMISTREAMCLK0_GATE_DISABLE;\ + type HDMISTREAMCLK1_GATE_DISABLE;\ + type HDMISTREAMCLK2_GATE_DISABLE;\ + type HDMISTREAMCLK3_GATE_DISABLE;\ + type HDMISTREAMCLK4_GATE_DISABLE;\ + type HDMISTREAMCLK5_GATE_DISABLE;\ + type SYMCLKA_CLOCK_ENABLE;\ + type SYMCLKB_CLOCK_ENABLE;\ + type SYMCLKC_CLOCK_ENABLE;\ + type SYMCLKD_CLOCK_ENABLE;\ + type SYMCLKE_CLOCK_ENABLE;\ + type SYMCLKA_FE_EN;\ + type SYMCLKB_FE_EN;\ + type SYMCLKC_FE_EN;\ + type SYMCLKD_FE_EN;\ + type SYMCLKE_FE_EN;\ + type SYMCLKA_SRC_SEL;\ + type SYMCLKB_SRC_SEL;\ + type SYMCLKC_SRC_SEL;\ + type SYMCLKD_SRC_SEL;\ + type SYMCLKE_SRC_SEL;\ + type SYMCLKA_FE_SRC_SEL;\ + type SYMCLKB_FE_SRC_SEL;\ + type SYMCLKC_FE_SRC_SEL;\ + type SYMCLKD_FE_SRC_SEL;\ + type SYMCLKE_FE_SRC_SEL; + struct dccg_shift { DCCG_REG_FIELD_LIST(uint8_t) DCCG3_REG_FIELD_LIST(uint8_t) DCCG31_REG_FIELD_LIST(uint8_t) DCCG314_REG_FIELD_LIST(uint8_t) DCCG32_REG_FIELD_LIST(uint8_t) + DCCG35_REG_FIELD_LIST(uint8_t) }; struct dccg_mask { @@ -254,6 +308,7 @@ struct dccg_mask { DCCG31_REG_FIELD_LIST(uint32_t) DCCG314_REG_FIELD_LIST(uint32_t) DCCG32_REG_FIELD_LIST(uint32_t) + DCCG35_REG_FIELD_LIST(uint32_t) }; struct dccg_registers { @@ -292,6 +347,15 @@ struct dccg_registers { uint32_t DCCG_GATE_DISABLE_CNTL4; uint32_t OTG_PIXEL_RATE_DIV; uint32_t DTBCLK_P_CNTL; + uint32_t DPPCLK_CTRL; + uint32_t DCCG_GATE_DISABLE_CNTL5; + uint32_t DCCG_GATE_DISABLE_CNTL6; + uint32_t DCCG_GLOBAL_FGCG_REP_CNTL; + uint32_t SYMCLKA_CLOCK_ENABLE; + uint32_t SYMCLKB_CLOCK_ENABLE; + uint32_t SYMCLKC_CLOCK_ENABLE; + uint32_t SYMCLKD_CLOCK_ENABLE; + uint32_t SYMCLKE_CLOCK_ENABLE; }; struct dcn_dccg { diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c index 971fa8bf6d1f..ad82f19fe36a 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c +++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c @@ -94,7 +94,7 @@ static int find_free_gsl_group(const struct dc *dc) * gsl_0 <=> pipe_ctx->stream_res.gsl_group == 1 * Using a magic value like -1 would require tracking all inits/resets */ -static void dcn20_setup_gsl_group_as_lock( + void dcn20_setup_gsl_group_as_lock( const struct dc *dc, struct pipe_ctx *pipe_ctx, bool enable) @@ -1735,7 +1735,11 @@ static void dcn20_program_pipe( hws->funcs.update_odm(dc, context, pipe_ctx); if (pipe_ctx->update_flags.bits.enable) { - dcn20_enable_plane(dc, pipe_ctx, context); + if (hws->funcs.enable_plane) + hws->funcs.enable_plane(dc, pipe_ctx, context); + else + dcn20_enable_plane(dc, pipe_ctx, context); + if (dc->res_pool->hubbub->funcs->force_wm_propagate_to_pipes) dc->res_pool->hubbub->funcs->force_wm_propagate_to_pipes(dc->res_pool->hubbub); } diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.h b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.h index 01901b08644c..351b66e3f38b 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.h +++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.h @@ -150,5 +150,10 @@ void dcn20_set_disp_pattern_generator(const struct dc *dc, const struct tg_color *solid_color, int width, int height, int offset); +void dcn20_setup_gsl_group_as_lock( + const struct dc *dc, + struct pipe_ctx *pipe_ctx, + bool enable); + #endif /* __DC_HWSS_DCN20_H__ */ diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer_private.h b/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer_private.h index 4ca4192c1e12..82c592166875 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer_private.h +++ b/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer_private.h @@ -152,6 +152,8 @@ struct hwseq_private_funcs { void (*PLAT_58856_wa)(struct dc_state *context, struct pipe_ctx *pipe_ctx); void (*setup_hpo_hw_control)(const struct dce_hwseq *hws, bool enable); + void (*enable_plane)(struct dc *dc, struct pipe_ctx *pipe_ctx, + struct dc_state *context); #ifdef CONFIG_DRM_AMD_DC_FP void (*program_mall_pipe_config)(struct dc *dc, struct dc_state *context); void (*update_force_pstate)(struct dc *dc, struct dc_state *context); -- 2.20.1