From 9ec525729f59e2885e6f06f6c1cd56665d519b1b Mon Sep 17 00:00:00 2001 From: Ben Skeggs Date: Mon, 22 Jun 2020 11:31:56 +1000 Subject: [PATCH] drm/nouveau/fbcon: convert fillrect() to new push macros Signed-off-by: Ben Skeggs Reviewed-by: Lyude Paul --- drivers/gpu/drm/nouveau/nouveau_dma.h | 1 - drivers/gpu/drm/nouveau/nv04_fbcon.c | 18 ++++++------- drivers/gpu/drm/nouveau/nv50_fbcon.c | 37 +++++++++++++++------------ drivers/gpu/drm/nouveau/nvc0_fbcon.c | 37 +++++++++++++++------------ 4 files changed, 48 insertions(+), 45 deletions(-) diff --git a/drivers/gpu/drm/nouveau/nouveau_dma.h b/drivers/gpu/drm/nouveau/nouveau_dma.h index edc5a3b722e6..bb1b89adaf73 100644 --- a/drivers/gpu/drm/nouveau/nouveau_dma.h +++ b/drivers/gpu/drm/nouveau/nouveau_dma.h @@ -49,7 +49,6 @@ void nv50_dma_push(struct nouveau_channel *, u64 addr, int length); enum { NvSubSw = 1, NvSubImageBlit = 2, - NvSubGdiRect = 3, NvSub2D = 3, /* DO NOT CHANGE - hardcoded for kepler gr fifo */ NvSubCopy = 4, /* DO NOT CHANGE - hardcoded for kepler gr fifo */ diff --git a/drivers/gpu/drm/nouveau/nv04_fbcon.c b/drivers/gpu/drm/nouveau/nv04_fbcon.c index 91be0d1827c3..397dd1799613 100644 --- a/drivers/gpu/drm/nouveau/nv04_fbcon.c +++ b/drivers/gpu/drm/nouveau/nv04_fbcon.c @@ -54,24 +54,22 @@ nv04_fbcon_fillrect(struct fb_info *info, const struct fb_fillrect *rect) struct nouveau_fbdev *nfbdev = info->par; struct nouveau_drm *drm = nouveau_drm(nfbdev->helper.dev); struct nouveau_channel *chan = drm->channel; + struct nvif_push *push = chan->chan.push; int ret; - ret = RING_SPACE(chan, 7); + ret = PUSH_WAIT(push, 7); if (ret) return ret; - BEGIN_NV04(chan, NvSubGdiRect, 0x02fc, 1); - OUT_RING(chan, (rect->rop != ROP_COPY) ? 1 : 3); - BEGIN_NV04(chan, NvSubGdiRect, 0x03fc, 1); + PUSH_NVSQ(push, NV04A, 0x02fc, (rect->rop != ROP_COPY) ? 1 : 3); if (info->fix.visual == FB_VISUAL_TRUECOLOR || info->fix.visual == FB_VISUAL_DIRECTCOLOR) - OUT_RING(chan, ((uint32_t *)info->pseudo_palette)[rect->color]); + PUSH_NVSQ(push, NV04A, 0x03fc, ((uint32_t *)info->pseudo_palette)[rect->color]); else - OUT_RING(chan, rect->color); - BEGIN_NV04(chan, NvSubGdiRect, 0x0400, 2); - OUT_RING(chan, (rect->dx << 16) | rect->dy); - OUT_RING(chan, (rect->width << 16) | rect->height); - FIRE_RING(chan); + PUSH_NVSQ(push, NV04A, 0x03fc, rect->color); + PUSH_NVSQ(push, NV04A, 0x0400, (rect->dx << 16) | rect->dy, + 0x0404, (rect->width << 16) | rect->height); + PUSH_KICK(push); return 0; } diff --git a/drivers/gpu/drm/nouveau/nv50_fbcon.c b/drivers/gpu/drm/nouveau/nv50_fbcon.c index dd20485e38d9..6d122b045f4c 100644 --- a/drivers/gpu/drm/nouveau/nv50_fbcon.c +++ b/drivers/gpu/drm/nouveau/nv50_fbcon.c @@ -35,32 +35,35 @@ nv50_fbcon_fillrect(struct fb_info *info, const struct fb_fillrect *rect) struct nouveau_fbdev *nfbdev = info->par; struct nouveau_drm *drm = nouveau_drm(nfbdev->helper.dev); struct nouveau_channel *chan = drm->channel; + struct nvif_push *push = chan->chan.push; + u32 colour; int ret; - ret = RING_SPACE(chan, rect->rop == ROP_COPY ? 7 : 11); + if (info->fix.visual == FB_VISUAL_TRUECOLOR || + info->fix.visual == FB_VISUAL_DIRECTCOLOR) + colour = ((uint32_t *)info->pseudo_palette)[rect->color]; + else + colour = rect->color; + + ret = PUSH_WAIT(push, rect->rop == ROP_COPY ? 7 : 11); if (ret) return ret; if (rect->rop != ROP_COPY) { - BEGIN_NV04(chan, NvSub2D, 0x02ac, 1); - OUT_RING(chan, 1); + PUSH_NVSQ(push, NV502D, 0x02ac, 1); } - BEGIN_NV04(chan, NvSub2D, 0x0588, 1); - if (info->fix.visual == FB_VISUAL_TRUECOLOR || - info->fix.visual == FB_VISUAL_DIRECTCOLOR) - OUT_RING(chan, ((uint32_t *)info->pseudo_palette)[rect->color]); - else - OUT_RING(chan, rect->color); - BEGIN_NV04(chan, NvSub2D, 0x0600, 4); - OUT_RING(chan, rect->dx); - OUT_RING(chan, rect->dy); - OUT_RING(chan, rect->dx + rect->width); - OUT_RING(chan, rect->dy + rect->height); + + PUSH_NVSQ(push, NV502D, 0x0588, colour); + PUSH_NVSQ(push, NV502D, 0x0600, rect->dx, + 0x0604, rect->dy, + 0x0608, rect->dx + rect->width, + 0x060c, rect->dy + rect->height); + if (rect->rop != ROP_COPY) { - BEGIN_NV04(chan, NvSub2D, 0x02ac, 1); - OUT_RING(chan, 3); + PUSH_NVSQ(push, NV502D, 0x02ac, 3); } - FIRE_RING(chan); + + PUSH_KICK(push); return 0; } diff --git a/drivers/gpu/drm/nouveau/nvc0_fbcon.c b/drivers/gpu/drm/nouveau/nvc0_fbcon.c index ae88f6683f62..414025a43540 100644 --- a/drivers/gpu/drm/nouveau/nvc0_fbcon.c +++ b/drivers/gpu/drm/nouveau/nvc0_fbcon.c @@ -35,32 +35,35 @@ nvc0_fbcon_fillrect(struct fb_info *info, const struct fb_fillrect *rect) struct nouveau_fbdev *nfbdev = info->par; struct nouveau_drm *drm = nouveau_drm(nfbdev->helper.dev); struct nouveau_channel *chan = drm->channel; + struct nvif_push *push = chan->chan.push; + u32 colour; int ret; - ret = RING_SPACE(chan, rect->rop == ROP_COPY ? 7 : 11); + if (info->fix.visual == FB_VISUAL_TRUECOLOR || + info->fix.visual == FB_VISUAL_DIRECTCOLOR) + colour = ((uint32_t *)info->pseudo_palette)[rect->color]; + else + colour = rect->color; + + ret = PUSH_WAIT(push, rect->rop == ROP_COPY ? 7 : 9); if (ret) return ret; if (rect->rop != ROP_COPY) { - BEGIN_NVC0(chan, NvSub2D, 0x02ac, 1); - OUT_RING (chan, 1); + PUSH_NVIM(push, NV902D, 0x02ac, 1); } - BEGIN_NVC0(chan, NvSub2D, 0x0588, 1); - if (info->fix.visual == FB_VISUAL_TRUECOLOR || - info->fix.visual == FB_VISUAL_DIRECTCOLOR) - OUT_RING (chan, ((uint32_t *)info->pseudo_palette)[rect->color]); - else - OUT_RING (chan, rect->color); - BEGIN_NVC0(chan, NvSub2D, 0x0600, 4); - OUT_RING (chan, rect->dx); - OUT_RING (chan, rect->dy); - OUT_RING (chan, rect->dx + rect->width); - OUT_RING (chan, rect->dy + rect->height); + + PUSH_NVSQ(push, NV902D, 0x0588, colour); + PUSH_NVSQ(push, NV902D, 0x0600, rect->dx, + 0x0604, rect->dy, + 0x0608, rect->dx + rect->width, + 0x060c, rect->dy + rect->height); + if (rect->rop != ROP_COPY) { - BEGIN_NVC0(chan, NvSub2D, 0x02ac, 1); - OUT_RING (chan, 3); + PUSH_NVIM(push, NV902D, 0x02ac, 3); } - FIRE_RING(chan); + + PUSH_KICK(push); return 0; } -- 2.20.1