From 420c6a6f65f4856f77dba278ae32e2701d8838f3 Mon Sep 17 00:00:00 2001 From: Daniele Ceraolo Spurio Date: Tue, 27 Jun 2023 15:28:56 -0700 Subject: [PATCH] drm/xe: fix HuC FW ordering for DG1 The firmware definitions must be ordered based on platform, from newer to older, which means that the DG1 FW must come before the ADL one. Link: https://gitlab.freedesktop.org/drm/intel/-/issues/8699 Signed-off-by: Daniele Ceraolo Spurio Reviewed-by: Matthew Brost Link: https://lore.kernel.org/r/20230627222856.3165647-1-daniele.ceraolospurio@intel.com Signed-off-by: Rodrigo Vivi --- drivers/gpu/drm/xe/xe_uc_fw.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/xe/xe_uc_fw.c b/drivers/gpu/drm/xe/xe_uc_fw.c index 2b9b9b4a6711..bc63c0d3e33a 100644 --- a/drivers/gpu/drm/xe/xe_uc_fw.c +++ b/drivers/gpu/drm/xe/xe_uc_fw.c @@ -111,9 +111,9 @@ struct fw_blobs_by_type { fw_def(TIGERLAKE, major_ver(i915, guc, tgl, 70, 5)) #define XE_HUC_FIRMWARE_DEFS(fw_def, mmp_ver, no_ver) \ + fw_def(DG1, no_ver(i915, huc, dg1)) \ fw_def(ALDERLAKE_P, no_ver(i915, huc, tgl)) \ fw_def(ALDERLAKE_S, no_ver(i915, huc, tgl)) \ - fw_def(DG1, no_ver(i915, huc, dg1)) \ fw_def(ROCKETLAKE, no_ver(i915, huc, tgl)) \ fw_def(TIGERLAKE, no_ver(i915, huc, tgl)) -- 2.20.1