From 2267a195e28cc438cb45936c4562f958502d4038 Mon Sep 17 00:00:00 2001 From: Dillon Varone Date: Wed, 13 Apr 2022 17:54:19 -0400 Subject: [PATCH] drm/amd/display: Disable DTB Ref Clock Switching in dcn32 [How & Why] To be enabled once PMFW supports it. Signed-off-by: Dillon Varone Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c index 774de29fa532..f147c65137c6 100644 --- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c +++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c @@ -607,6 +607,10 @@ void dcn32_clk_mgr_construct( if (clk_mgr->base.dentist_vco_freq_khz == 0) clk_mgr->base.dentist_vco_freq_khz = 4300000; /* Updated as per HW docs */ + if (clk_mgr->dccg->ref_dtbclk_khz != clk_mgr->base.boot_snapshot.dtbclk) { + clk_mgr->dccg->ref_dtbclk_khz = clk_mgr->base.boot_snapshot.dtbclk; + } + if (clk_mgr->base.boot_snapshot.dprefclk != 0) { //ASSERT(clk_mgr->base.dprefclk_khz == clk_mgr->base.boot_snapshot.dprefclk); //clk_mgr->base.dprefclk_khz = clk_mgr->base.boot_snapshot.dprefclk; -- 2.20.1