clk: mediatek: Add new clock driver to handle FHCTL hardware
authorJohnson Wang <johnson.wang@mediatek.com>
Mon, 21 Nov 2022 12:29:56 +0000 (20:29 +0800)
committerChen-Yu Tsai <wenst@chromium.org>
Tue, 29 Nov 2022 06:43:07 +0000 (14:43 +0800)
commitd7964de8a8ea800910fdd4e365c42a9e7d5c54aa
tree96fb0279f6b4cee4b4dd42474b3811017139d807
parentcfcefe36bf939107eeba7b1114e3d82e31f92893
clk: mediatek: Add new clock driver to handle FHCTL hardware

To implement frequency hopping and spread spectrum clocking
function, we introduce new clock type and APIs to handle
FHCTL hardware.

Co-developed-by: Edward-JW Yang <edward-jw.yang@mediatek.com>
Signed-off-by: Edward-JW Yang <edward-jw.yang@mediatek.com>
Signed-off-by: Johnson Wang <johnson.wang@mediatek.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Link: https://lore.kernel.org/r/20221121122957.21611-4-johnson.wang@mediatek.com
Signed-off-by: Chen-Yu Tsai <wenst@chromium.org>
drivers/clk/mediatek/Kconfig
drivers/clk/mediatek/Makefile
drivers/clk/mediatek/clk-fhctl.c [new file with mode: 0644]
drivers/clk/mediatek/clk-fhctl.h [new file with mode: 0644]
drivers/clk/mediatek/clk-pllfh.c [new file with mode: 0644]
drivers/clk/mediatek/clk-pllfh.h [new file with mode: 0644]