MIPS: Netlogic: Add MSI support for XLP
authorJayachandran C <jchandra@broadcom.com>
Sat, 21 Dec 2013 11:22:13 +0000 (16:52 +0530)
committerRalf Baechle <ralf@linux-mips.org>
Fri, 24 Jan 2014 21:39:46 +0000 (22:39 +0100)
commitc24a8a7a99885d5b986f38f6631f69e7794a3e5e
treea0d6702fc1c45cba157a5734215c509fa4b216c6
parent27547abf36af7964b53a8c9265e266df692d4806
MIPS: Netlogic: Add MSI support for XLP

Add MSI chip and MSIX chip definitions.

For MSI, we map the link interrupt to a MSI link IRQ which will
do a second level of dispatch based on the MSI status register.

The MSI chip definitions use the MSI enable register to enable
and disable the MSI irqs.

For MSI-X, we split the 32 available MSI-X vectors across the
four PCIe links (8 each). These PIC interrupts generate an IRQ
per link which uses a second level dispatch as well.

The MSI-X chip definition uses the standard functions to enable
and disable interrupts.

Signed-off-by: Jayachandran C <jchandra@broadcom.com>
Signed-off-by: John Crispin <blogic@openwrt.org>
Patchwork: http://patchwork.linux-mips.org/patch/6270/
arch/mips/Kconfig
arch/mips/include/asm/mach-netlogic/irq.h
arch/mips/include/asm/netlogic/common.h
arch/mips/include/asm/netlogic/xlp-hal/pcibus.h
arch/mips/include/asm/netlogic/xlp-hal/pic.h
arch/mips/include/asm/netlogic/xlp-hal/xlp.h
arch/mips/netlogic/common/irq.c
arch/mips/netlogic/xlp/nlm_hal.c
arch/mips/pci/Makefile
arch/mips/pci/msi-xlp.c [new file with mode: 0644]
arch/mips/pci/pci-xlp.c