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dt-bindings: interrupt-controller: RISC-V local interrupt controller
authorPalmer Dabbelt <palmer@dabbelt.com>
Tue, 27 Jun 2017 05:07:50 +0000 (22:07 -0700)
committerPalmer Dabbelt <palmer@sifive.com>
Mon, 13 Aug 2018 16:36:02 +0000 (09:36 -0700)
commitb67bc7cb408816b94224a74dff9868d2a38bf30c
treeb34c3971cbc2e70e716a6cbbea905da4142d8001tree
parent4c42ae4f6ab78f9ce3fa7e66de44f666733288dacommit | diff
dt-bindings: interrupt-controller: RISC-V local interrupt controller

Add documentation on the RISC-V local interrupt controller, which is a
per-hart interrupt controller that manages all interrupts entering a
RISC-V hart.  This interrupt controller is present on all RISC-V systems.

Signed-off-by: Palmer Dabbelt <palmer@dabbelt.com>
[hch: minor cleanups]
Signed-off-by: Christoph Hellwig <hch@lst.de>
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
Documentation/devicetree/bindings/interrupt-controller/riscv,cpu-intc.txt [new file with mode: 0644] blob
MicroBlaze GIT Repository