drm/i915/tgl: Access the right register when handling PSR interruptions
authorJosé Roberto de Souza <jose.souza@intel.com>
Wed, 4 Sep 2019 21:34:15 +0000 (14:34 -0700)
committerJosé Roberto de Souza <jose.souza@intel.com>
Thu, 5 Sep 2019 00:03:35 +0000 (17:03 -0700)
commit8241cfbe67f4082eee5fc72e5a8025c5b58c2ddf
tree2c14871c89366e5cc8433a66ed8a5f81e6380904
parent2f3b87124b9f08518b43abf2266035dd22fdbd3c
drm/i915/tgl: Access the right register when handling PSR interruptions

For older gens PSR IIR and IMR have fixed addresses. From TGL onwards those
registers moved to each transcoder offset. The bits for the registers
are defined without an offset per transcoder as right now we have one
register per transcoder. So add a fake "trans_shift" when calculating
the bits offsets: it will be 0 for gen12+ and psr.transcoder otherwise.

v2 (Lucas): change the implementation to use trans_shift instead of
getting each bit value with a different macro

Cc: Imre Deak <imre.deak@intel.com>
Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20190904213419.27547-3-jose.souza@intel.com
drivers/gpu/drm/i915/display/intel_psr.c
drivers/gpu/drm/i915/i915_irq.c
drivers/gpu/drm/i915/i915_reg.h