KVM: arm/arm64: Support chained PMU counters
authorAndrew Murray <andrew.murray@arm.com>
Mon, 17 Jun 2019 19:01:05 +0000 (20:01 +0100)
committerMarc Zyngier <marc.zyngier@arm.com>
Fri, 5 Jul 2019 12:56:22 +0000 (13:56 +0100)
commit80f393a23be68e2f8a0f74258d6155438c200bbd
treec07e0e47ad5c14a8cbfef8cfe9a0763faf153254
parent218907cbc2b82419c70180610163c987d4764b27
KVM: arm/arm64: Support chained PMU counters

ARMv8 provides support for chained PMU counters, where an event type
of 0x001E is set for odd-numbered counters, the event counter will
increment by one for each overflow of the preceding even-numbered
counter. Let's emulate this in KVM by creating a 64 bit perf counter
when a user chains two emulated counters together.

For chained events we only support generating an overflow interrupt
on the high counter. We use the attributes of the low counter to
determine the attributes of the perf event.

Suggested-by: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Andrew Murray <andrew.murray@arm.com>
Reviewed-by: Julien Thierry <julien.thierry@arm.com>
Reviewed-by: Suzuki K Poulose <suzuki.poulose@arm.com>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
include/kvm/arm_pmu.h
virt/kvm/arm/pmu.c