perf/x86: Support counter mask
authorKan Liang <kan.liang@linux.intel.com>
Wed, 26 Jun 2024 14:35:34 +0000 (07:35 -0700)
committerPeter Zijlstra <peterz@infradead.org>
Thu, 4 Jul 2024 14:00:36 +0000 (16:00 +0200)
commit722e42e45c2f1c6d1adec7813651dba5139f52f4
tree6110b0fd8d8877d8d9e9a9928ab5ff7d430e29a8
parenta23eb2fc1d818cdac9b31f032842d55483a6a040
perf/x86: Support counter mask

The current perf assumes that both GP and fixed counters are contiguous.
But it's not guaranteed on newer Intel platforms or in a virtualization
environment.

Use the counter mask to replace the number of counters for both GP and
the fixed counters. For the other ARCHs or old platforms which don't
support a counter mask, using GENMASK_ULL(num_counter - 1, 0) to
replace. There is no functional change for them.

The interface to KVM is not changed. The number of counters still be
passed to KVM. It can be updated later separately.

Signed-off-by: Kan Liang <kan.liang@linux.intel.com>
Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Reviewed-by: Andi Kleen <ak@linux.intel.com>
Reviewed-by: Ian Rogers <irogers@google.com>
Link: https://lkml.kernel.org/r/20240626143545.480761-3-kan.liang@linux.intel.com
arch/x86/events/amd/core.c
arch/x86/events/core.c
arch/x86/events/intel/core.c
arch/x86/events/intel/ds.c
arch/x86/events/intel/knc.c
arch/x86/events/intel/p4.c
arch/x86/events/intel/p6.c
arch/x86/events/perf_event.h
arch/x86/events/zhaoxin/core.c