drm/i915/ringbuffer: Delay after EMIT_INVALIDATE for gen4/gen5
authorChris Wilson <chris@chris-wilson.co.uk>
Mon, 5 Nov 2018 09:43:05 +0000 (09:43 +0000)
committerChris Wilson <chris@chris-wilson.co.uk>
Wed, 7 Nov 2018 15:31:45 +0000 (15:31 +0000)
commit55f99bf2a9c331838c981694bc872cd1ec4070b2
tree2805129c2f9e497f547b0fe40f109681a33d685b
parent64e3d12f769d60eaee6d2e53a9b7f0b3814f32ed
drm/i915/ringbuffer: Delay after EMIT_INVALIDATE for gen4/gen5

Exercising the gpu reloc path strenuously revealed an issue where the
updated relocations (from MI_STORE_DWORD_IMM) were not being observed
upon execution. After some experiments with adding pipecontrols (a lot
of pipecontrols (32) as gen4/5 do not have a bit to wait on earlier pipe
controls or even the current on), it was discovered that we merely
needed to delay the EMIT_INVALIDATE by several flushes. It is important
to note that it is the EMIT_INVALIDATE as opposed to the EMIT_FLUSH that
needs the delay as opposed to what one might first expect -- that the
delay is required for the TLB invalidation to take effect (one presumes
to purge any CS buffers) as opposed to a delay after flushing to ensure
the writes have landed before triggering invalidation.

Testcase: igt/gem_tiled_fence_blits
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: stable@vger.kernel.org
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20181105094305.5767-1-chris@chris-wilson.co.uk
drivers/gpu/drm/i915/intel_ringbuffer.c