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drm/amd/display: Do not set DRR on pipe commit
authorWesley Chalmers <Wesley.Chalmers@amd.com>
Fri, 4 Nov 2022 02:29:31 +0000 (22:29 -0400)
committerAlex Deucher <alexander.deucher@amd.com>
Wed, 8 Feb 2023 22:15:14 +0000 (17:15 -0500)
commit4f1b5e739dfd1edde33329e3f376733a131fb1ff
tree035acfde872cb311fb38a3605b5b97ace5ca298ctree
parent642f1b405255ec5574eb20a3f72e29676b94679ccommit | diff
drm/amd/display: Do not set DRR on pipe commit

[WHY]
Writing to DRR registers such as OTG_V_TOTAL_MIN on the same frame as a
pipe commit can cause underflow.

[HOW]
Defer all DPP adjustment requests till optimized_required is false.

Reviewed-by: Jun Lei <Jun.Lei@amd.com>
Acked-by: Qingqing Zhuo <qingqing.zhuo@amd.com>
Signed-off-by: Wesley Chalmers <Wesley.Chalmers@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hwseq.c diff | blob | history
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