mmc: sdhci-of-esdhc: workaround for unreliable pulse width detection
authorYangbo Lu <yangbo.lu@nxp.com>
Fri, 23 Nov 2018 03:15:37 +0000 (11:15 +0800)
committerUlf Hansson <ulf.hansson@linaro.org>
Mon, 17 Dec 2018 07:26:24 +0000 (08:26 +0100)
commit48e304cc1970b65f43c0d2f82aaf48285f0eccd2
treecd7a239f97a279cacd664202a9e3f5ddfb74caa4
parent58d0bf843b49fa99588ac9f85178bd8dfd651b53
mmc: sdhci-of-esdhc: workaround for unreliable pulse width detection

This was a SoC issue on LX2160A Rev1.0.
eSDHC_DLLCFG1[DLL_PD_PULSE_STRETCH_SEL] must be set to 0 to
get 4 delay cells in the pulse width detection logic for eMMC
HS400 mode. Otherwise it would cause unexpected HS400 issue.
This patch is to clear this bit always for affected SoC when
reset for all, since this bit doesn't affect other speed modes.

Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
drivers/mmc/host/sdhci-esdhc.h
drivers/mmc/host/sdhci-of-esdhc.c