drm/xe: Use topology to determine page fault queue size
authorStuart Summers <stuart.summers@intel.com>
Sat, 17 Aug 2024 02:47:31 +0000 (02:47 +0000)
committerMatthew Brost <matthew.brost@intel.com>
Tue, 20 Aug 2024 16:45:51 +0000 (09:45 -0700)
commit3338e4f90c143cf32f77d64f464cb7f2c2d24700
treed51b28ac77ec0c29b7ec4d951bae576f47561f0b
parent7586fc52b14e0b8edd0d1f8a434e0de2078b7b2b
drm/xe: Use topology to determine page fault queue size

Currently the page fault queue size is hard coded. However
the hardware supports faulting for each EU and each CS.
For some applications running on hardware with a large
number of EUs and CSs, this can result in an overflow of
the page fault queue.

Add a small calculation to determine the page fault queue
size based on the number of EUs and CSs in the platform as
detmined by fuses.

Signed-off-by: Stuart Summers <stuart.summers@intel.com>
Reviewed-by: Matthew Brost <matthew.brost@intel.com>
Signed-off-by: Matthew Brost <matthew.brost@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/24d582a3b48c97793b8b6a402f34b4b469471636.1723862633.git.stuart.summers@intel.com
drivers/gpu/drm/xe/xe_gt_pagefault.c
drivers/gpu/drm/xe/xe_gt_types.h