drm/amd/display: Set DSC before DIG front-end is connected to its back-end
authorNikola Cornij <nikola.cornij@amd.com>
Wed, 17 Jul 2019 23:02:14 +0000 (19:02 -0400)
committerAlex Deucher <alexander.deucher@amd.com>
Thu, 15 Aug 2019 15:54:53 +0000 (10:54 -0500)
commit1a9e3d4569fc9a9a1cbfb14cacf3268114646ab6
treeadebad7ceb20beba78e1676bb727ae318cf9cc7b
parent7470673340b118b744e629383e8374ced4100b84
drm/amd/display: Set DSC before DIG front-end is connected to its back-end

[why]
At the time DIG FE is connected to its BE, the clocks in OTG are enabled and
PHY will also be set up. When DSC has to be used to fit the stream into the
available bandwidth, without DSC being set DIG could get exposed to the
higer bandwidth it (or link) could handle. This causes the HW to "reject"
video enable setup (the register shows that video enable was attempted, but
the status bit shows it as disabled).

[how]
- Separate DSC setup into DSC register config and DSC PPS SDP setup

- Move most of the DSC setup (register config) to before
  dcn10_link_encoder_connect_dig_be_to_fe() is  called

- Set up DSC PPS SDP after DIG FE is connected to its BE. This is because
  setting DSC PPS SDP before that has no effect.

Signed-off-by: Nikola Cornij <nikola.cornij@amd.com>
Reviewed-by: Jun Lei <Jun.Lei@amd.com>
Acked-by: Leo Li <sunpeng.li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drivers/gpu/drm/amd/display/dc/core/dc_link.c
drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c
drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c
drivers/gpu/drm/amd/display/dc/dcn20/dcn20_stream_encoder.c
drivers/gpu/drm/amd/display/dc/inc/dc_link_dp.h
drivers/gpu/drm/amd/display/dc/inc/hw/dsc.h
drivers/gpu/drm/amd/display/dc/inc/hw/stream_encoder.h