Arnd Bergmann [Fri, 14 Apr 2023 15:42:27 +0000 (17:42 +0200)]
Merge tag 'sunxi-dt-for-6.4-1' of https://git./linux/kernel/git/sunxi/linux into soc/dt
- added D1 crypto node
- enabled DVFS on OrangePi PC2 board
- added GPIO line names on Nezha D1 board
- added suniv USB nodes and enabled on licheepi-nano
- new suniv boards: PopStick v1.1 and Lctech Pi
- added Allwinner T113-s DTSI
- added MangoPi MQ-R T113-s board variant
- swapped DMA names for A23, A31, A33, D1, H3, H5, V3s
* tag 'sunxi-dt-for-6.4-1' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux:
riscv: dts: allwinner: d1: Switch dma-names order for snps,dw-apb-uart nodes
ARM: dts: sunxi: h3/h5: Switch dma-names order for snps,dw-apb-uart nodes
ARM: dts: sun8i: v3s: Switch dma-names order for snps,dw-apb-uart nodes
ARM: dts: sun8i: a23/a33: Switch dma-names order for snps,dw-apb-uart nodes
ARM: dts: sun6i: a31: Switch dma-names order for snps,dw-apb-uart nodes
ARM: dts: sunxi: add MangoPi MQ-R-T113 board
dt-bindings: arm: sunxi: document MangoPi MQ-R board names
ARM: dts: sunxi: add Allwinner T113-s SoC .dtsi
dts: add riscv include prefix link
ARM: dts: suniv: Add Lctech Pi F1C200s devicetree
ARM: dts: suniv: add device tree for PopStick v1.1
dt-binding: arm: sunxi: add two board compatible strings
dt-bindings: vendor-prefixes: add Source Parts and Lctech names
ARM: dts: suniv: licheepi-nano: enable USB
ARM: dts: suniv: add USB-related device nodes
riscv: dts: nezha-d1: add gpio-line-names
arm64: dts: allwinner: h5: OrangePi PC2: add OPP table to enable DVFS
riscv: dts: allwinner: d1: Add crypto engine node
Link: https://lore.kernel.org/r/20230408125156.GA17050@jernej-laptop
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Arnd Bergmann [Fri, 14 Apr 2023 15:28:58 +0000 (17:28 +0200)]
Merge tag 'imx-dt64-6.4' of git://git./linux/kernel/git/shawnguo/linux into soc/dt
i.MX arm64 device tree changes for 6.4:
- New board device trees: Apalis quadmax, DH electronics i.MX8M Plus
DHCOM and PDK3, Data Modul i.MX8M Plus eDM SBC, Colibri Aster and
Iris, etc.
- Add FlexSPI, BBNSM and TPM PWM devices for i.MX93 SoC.
- A series of imx8mq-librem5 udpates which includes minor fixes,
magnetometer, CSI/camera support, and powersaving improvements.
- Add Cadence USB3 support for i.MX8QXP.
- Add FlexCAN support for i.MX8QXP and i.MX8QM.
- Add UART DMA support for i.MX8MQ.
- Add GPT devices for i.MX8MP.
- Add VPU decoder and encoder support for i.MX8QM.
- Add display pipeline and PCIe EP support for i.MX8M family SoCs.
- A series from Peng Fan updating various i.MX8M device trees to pinctrl
nodes match DT schema.
- A series from Philippe Schenker improving colibri-imx8x device trees
in various aspects.
- Other random device tree updates.
* tag 'imx-dt64-6.4' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux: (87 commits)
arm64: dts: imx8mp: Add support for Data Modul i.MX8M Plus eDM SBC
arm64: dts: imx8mp: Add display pipeline components
arm64: dts: imx8mn: Add display pipeline components
arm64: dts: imx8mm: Add display pipeline components
arm64: dts: freescale: imx8qxp-mek: enable cadence usb3
arm64: dts: imx8qxp: add cadence usb3 support
arm64: dts: imx8mq-librem5: add missing #clock-cells
arm64: dts: imx8mm-prt8mm: update pinctrl to match dtschema
arm64: dts: imx8mn-bsh-smm: update pinctrl to match dtschema
arm64: dts: imx8mm-emcon: update pinctrl to match dtschema
arm64: dts: imx8mq-librem5: update pinctrl to match dtschema
arm64: dts: imx8mm-ddr4-evk: update gpmi pinctrl to match dtschema
arm64: dts: imx8mn-evk: update i2c pinctrl to match dtschema
arm64: dts: imx8mp: Add GPT blocks
arm64: dts: imx8-apalis-v1.1: drop ci-disable-lpm
arm64: dts: imx8dxl: drop clocks from scu clock controller
arm64: dts: imx8mp: verdin-yavia: drop disable-over-current
arm64: dts: imx8mq: tqma8mq-mba8mx: drop disable-over-current
arm64: dts: imx8mp: Add support for DH electronics i.MX8M Plus DHCOM and PDK3
arm64: dts: colibri-imx8x: Add iris v2 carrier board
...
Link: https://lore.kernel.org/r/20230408101928.280271-5-shawnguo@kernel.org
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Arnd Bergmann [Fri, 14 Apr 2023 15:27:25 +0000 (17:27 +0200)]
Merge tag 'imx-dt-6.4' of git://git./linux/kernel/git/shawnguo/linux into soc/dt
i.MX arm32 device tree changes for 6.4:
- New board device trees: Tolino Vison, chargebyte Tarragon,
new revision of the IOTA board.
- A couple of imx7d-remarkable2 update to enable cyttsp5 touch and
BD71815 PMIC.
- A series from Oleksij Rempel to configure Ethernet reference clock
from device tree.
- A series from Stefan Wahren to use label references for i.MX28 based
boards.
* tag 'imx-dt-6.4' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux: (31 commits)
ARM: dts: imx6ull: Add chargebyte Tarragon support
ARM: dts: imx: Add devicetree for Tolino Vison
ARM: dts: imx6dl-yapp43: Add support for new HW revision of the IOTA board
ARM: dts: imx6dl-yapp4: Remove unneeded status "okay"
ARM: dts: imx6dl-yapp4: Move status to the end of property list
ARM: dts: imx6dl-yapp4: Move phy reset into switch node
ARM: dts: imx28-tx28: add SPDX-License-Identifier
ARM: dts: imx28-ts4600: Convert to use label references
ARM: dts: imx28-evk: Convert to use label references
ARM: dts: imx28-duckbill-2: Include base board
ARM: dts: imx28-duckbill: Convert to use label references
ARM: dts: imx28-
cfa10036: Convert to use label references
ARM: dts: imx28-apx4devkit: Convert to use label references
ARM: dts: imx28-m28/sps1: Convert to use label references
ARM: dts: imx28-apf28: Convert to use label references
ARM: dts: imx7d-remarkable2: Enable the rohm,
bd71815
ARM: dts: imx7d-remarkable2: Enable the cyttsp5
ARM: dts: imx6dl-yapp4: Use reset-gpios property name
ARM: dts: imx6ul-prti6g: configure ethernet reference clock parent
ARM: dts: imx6ul: set enet_clk_ref to CLK_ENETx_REF_SEL
...
Link: https://lore.kernel.org/r/20230408101928.280271-4-shawnguo@kernel.org
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Arnd Bergmann [Fri, 14 Apr 2023 15:25:19 +0000 (17:25 +0200)]
Merge tag 'imx-bindings-6.4' of git://git./linux/kernel/git/shawnguo/linux into soc/dt
i.MX dt-bindings update for 6.4:
- Add vendor prefix for chargebyte.
- A bunch of new board compatibles: Tolino Vision, Toradex Apalis,
chargebyte Tarragon, i.MX8M Plus based boards from DH electronics
and Data Modul, etc.
- A series from Marek Vasut to improve blk-ctrl bindings.
* tag 'imx-bindings-6.4' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux:
dt-bindings: arm: Add Data Modul i.MX8M Plus eDM SBC
dt-bindings: arm: fsl: Add chargebyte Tarragon
dt-bindings: vendor-prefixes: add chargebyte
dt-bindings: soc: imx-blk-ctrl: Drop leading label in blk-ctrl in examples
dt-bindings: soc: imx8m-blk-ctrl: Rename blk_ctrl to blk-ctrl in examples
dt-bindings: arm: Add DH electronics i.MX8M Plus DHCOM on PDK3
dt-bindings: arm: fsl: add compatible string for Tolino Vision
dt-bindings: arm: fsl: Add Y Soft IOTA Phoenix, Lynx, Pegasus and Pegasus+
dt-bindings: arm: fsl: Add colibri-imx8x carrier boards
dt-bindings: soc: imx8mp-media-blk-ctrl: Add LDB subnode into schema and example
dt-bindings: soc: imx8mp-media-blk-ctrl: Align block controller example name
dt-bindings: arm: fsl: Fix copy-paste error in comment
dt-bindings: arm: fsl: add toradex,apalis-imx8 et al.
Arnd Bergmann [Fri, 14 Apr 2023 13:24:58 +0000 (15:24 +0200)]
Merge tag 'stm32-dt-for-v6.4-1' of git://git./linux/kernel/git/atorgue/stm32 into soc/dt
STM32 DT for v6.4, round 1
Highlights:
----------
- MPU:
- STM32MP13:
- Add FMC support.
- Add QSPI support.
- Add 8 UART instances nodes.
- Enable UART on STM32MP135F-DK:
-UART1/UART8 used on expansion connector.
-UART2 used for BT.
-UART4 used for console.
- STMP32MP15:
- Add STM32MP151 support ( documentation + machine).
- Uart fixes (slew rate, aliases clean-up).
- Fix GPU YAMl issue.
* tag 'stm32-dt-for-v6.4-1' of git://git.kernel.org/pub/scm/linux/kernel/git/atorgue/stm32:
ARM: stm32: add initial documentation for STM32MP151
ARM: dts: stm32: Add QSPI support on STM32MP13x SoC family
ARM: dts: stm32: add FMC support on STM32MP13x SoC family
ARM: dts: stm32: YAML validation fails for Argon Boards
ARM: dts: stm32: YAML validation fails for Odyssey Boards
ARM: dts: stm32: YAML validation fails for STM32MP15 ST Boards
ARM: dts: stm32: add uart nodes and uart aliases on stm32mp135f-dk
ARM: dts: stm32: add pins for usart2/1/4/8 in stm32mp13-pinctrl
ARM: dts: stm32: add uart nodes on stm32mp13
ARM: dts: stm32: clean uart aliases on stm32mp15xx-exx boards
ARM: dts: stm32: clean uart aliases on stm32mp15xx-dkx boards
ARM: dts: stm32: fix slew-rate of USART2 on stm32mp15xx-dkx
ARM: stm32: add support for STM32MP151
ARM: dts: stm32: fix spi1 pin assignment on stm32mp15
ARM: dts: stm32: drop invalid simple-panel compatible on stm32mp157c-lxa
ARM: dts: stm32: Add coprocessor detach mbox on stm32mp15xx-osd32 SoM
Link: https://lore.kernel.org/r/63987ed6-2813-15ff-e058-73312a730d61@foss.st.com
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Arnd Bergmann [Fri, 14 Apr 2023 13:24:00 +0000 (15:24 +0200)]
Merge tag 'riscv-dt-for-v6.4' of https://git./linux/kernel/git/conor/linux into soc/dt
RISC-V Devicetrees for v6.4
Microchip:
A "fix" for the system controller's regs on PolarFire SoC, adding a
missing reg property.
The patch had been sitting there for months and I only re-found it
recently, so you can guess how much of a "fix" it actually is. It'll
become needed when the system controller's QSPI gets added in the future,
but at present there's no urgency as the driver can handle both the
current and "fixed" versions.
StarFive:
Basic support for the JH7110 & the associated first-party dev board, the
VisionFive v2 (in two forms). There's a bunch of dt-bindings required
for this too, all of which have had input from the DT folk. There's
enough in this tag to boot to a console w/ an initramfs but little more.
The SoC supports some of the "new" bit manipulation instructions, which
is a good test for the recently added Zbb support in the kernel.
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
* tag 'riscv-dt-for-v6.4' of https://git.kernel.org/pub/scm/linux/kernel/git/conor/linux:
riscv: dts: starfive: Add StarFive JH7110 VisionFive 2 board device tree
riscv: dts: starfive: Add StarFive JH7110 pin function definitions
riscv: dts: starfive: Add initial StarFive JH7110 device tree
dt-bindings: riscv: Add SiFive S7 compatible
dt-bindings: interrupt-controller: Add StarFive JH7110 plic
dt-bindings: timer: Add StarFive JH7110 clint
dt-bindings: clock: Add StarFive JH7110 always-on clock and reset generator
dt-bindings: clock: Add StarFive JH7110 system clock and reset generator
riscv: dts: microchip: fix the mpfs' mailbox regs
riscv: dts: microchip: add mpfs specific macb reset support
Link: https://lore.kernel.org/r/20230406-shank-impromptu-3d483bbc249f@spud
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Arnd Bergmann [Fri, 14 Apr 2023 13:22:45 +0000 (15:22 +0200)]
Merge tag 'tegra-for-6.4-arm64-dt' of git://git./linux/kernel/git/tegra/linux into soc/dt
arm64: tegra: Device tree changes for v6.4-rc1
This adds support for the Jetson Orin NX and includes updates for Jetson
AGX Orin (audio codec, USB Type-C support).
* tag 'tegra-for-6.4-arm64-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux:
arm64: tegra: Add vccmq on Jetson TX2
arm64: tegra: Populate USB Type-C Controller for Jetson AGX Orin
arm64: tegra: Audio codec support on Jetson AGX Orin
arm64: tegra: Support Jetson Orin NX reference platform
arm64: tegra: Support Jetson Orin NX
dt-bindings: tegra: Document Jetson Orin NX reference platform
dt-bindings: tegra: Document Jetson Orin NX
arm64: tegra: Add DSU PMUs for Tegra234
arm64: tegra: Drop serial clock-names and reset-names
Link: https://lore.kernel.org/r/20230406124804.970394-6-thierry.reding@gmail.com
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Arnd Bergmann [Fri, 14 Apr 2023 13:21:05 +0000 (15:21 +0200)]
Merge tag 'tegra-for-6.4-arm-dt' of git://git./linux/kernel/git/tegra/linux into soc/dt
ARM: tegra: Device tree changes for v6.4-rc1
There are several fixes and cleanups here for some of the older Tegra
consumer devices.
* tag 'tegra-for-6.4-arm-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux:
ARM: tegra30: Use cpu* labels
ARM: tegra30: peripherals: Add 266.5MHz nodes
ARM: tegra: asus-tf101: Fix accelerometer mount matrix
ARM: tegra: transformers: Bind RT5631 sound nodes
ARM: tegra: transformers: Update WM8903 sound nodes
Link: https://lore.kernel.org/r/20230406124804.970394-5-thierry.reding@gmail.com
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Arnd Bergmann [Fri, 14 Apr 2023 13:20:35 +0000 (15:20 +0200)]
Merge tag 'tegra-for-6.4-dt-bindings' of git://git./linux/kernel/git/tegra/linux into soc/dt
dt-bindings: Changes for v6.4-rc1
This is a single patch that drops unneeded quotes from various Tegra-
related device tree bindings.
* tag 'tegra-for-6.4-dt-bindings' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux:
dt-bindings: arm: nvidia: Drop unneeded quotes
Link: https://lore.kernel.org/r/20230406124804.970394-4-thierry.reding@gmail.com
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Arnd Bergmann [Fri, 14 Apr 2023 13:19:25 +0000 (15:19 +0200)]
Merge tag 'asahi-soc-dt-6.4' of https://github.com/AsahiLinux/linux into soc/dt
Apple SoC DT updates for 6.4.
This time we have the M2 (t8112) device trees and compatible updates,
as well as a minor fix for PCIe ports on the prior models.
* tag 'asahi-soc-dt-6.4' of https://github.com/AsahiLinux/linux:
arm64: dts: apple: t600x: Disable unused PCIe ports
arm64: dts: apple: t8103: Disable unused PCIe ports
arm64: dts: apple: t8112: Initial t8112 (M2) device trees
dt-bindings: arm: apple: Add t8112 j413/j473/j493 compatibles
dt-bindings: clock: apple,nco: Add t8112-nco compatible
dt-bindings: i2c: apple,i2c: Add apple,t8112-i2c compatible
dt-bindings: pinctrl: apple,pinctrl: Add apple,t8112-pinctrl compatible
dt-bindings: pci: apple,pcie: Add t8112 support
dt-bindings: nvme: apple: Add apple,t8112-nvme-ans2 compatible string
dt-bindings: mailbox: apple,mailbox: Add t8112 compatibles
dt-bindings: iommu: apple,sart: Add apple,t8112-sart compatible string
dt-bindings: interrupt-controller: apple,aic2: Add apple,t8112-aic compatible
dt-bindings: arm: cpus: Add apple,avalanche & blizzard compatibles
dt-bindings: watchdog: apple,wdt: Add t8112-wdt compatible
dt-bindings: arm: apple: apple,pmgr: Add t8112-pmgr compatible
dt-bindings: power: apple,pmgr-pwrstate: Add t8112 compatible
Link: https://lore.kernel.org/r/7263df01-aebc-2db5-f074-4805e0ae9fbc@marcan.st
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Arnd Bergmann [Fri, 14 Apr 2023 13:16:22 +0000 (15:16 +0200)]
Merge tag 'samsung-dt-6.4' of https://git./linux/kernel/git/krzk/linux into soc/dt
Samsung DTS ARM changes for v6.4
1. Several cleanups and improvements as a result of dtbs_checks: align
node names with bindings, drop incorrect properties, fix clock-names,
add missing "ports" node.
2. Move DP and MIPI phys to PMU node (DTS with binding change).
3. Drop old MSHC aliases (while adding proper mmc-ddr-1_8v which was
selected by the driver based on the MSHC alias) and add generic MMC
aliases in each board. The aliases match known numbering in
the schematics.
* tag 'samsung-dt-6.4' of https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux:
dt-bindings: soc: samsung: exynos-pmu: allow phys as child on Exynos3 and Exynos4
ARM: dts: exynos: add mmc aliases
ARM: dts: exynos: replace mshc0 alias with mmc-ddr-1_8v property
ARM: dts: exynos: fix MCT compatible in Universal C210
ARM: dts: exynos: move DP and MIPI phys to PMU node in Exynos5250
ARM: dts: exynos: move DP and MIPI phys to PMU node in Exynos5420
ARM: dts: exynos: move MIPI phy to PMU node in Exynos4
ARM: dts: exynos: move MIPI phy to PMU node in Exynos3250
ARM: dts: exynos: drop unused samsung,camclk-out property in Midas
ARM: dts: s5pv210: correct MIPI CSIS clock name
ARM: dts: exynos: correct whitespace in Midas
ARM: dts: exynos: fix WM8960 clock name in Itop Elite
ARM: dts: exynos: add ports to TC358764 bridge on Arndale
ARM: dts: exynos: drop fake align STMPE properties in P4 Note
ARM: dts: exynos: align STMPE ADC node name with bindings in P4 Note
Link: https://lore.kernel.org/r/20230405080438.156805-2-krzysztof.kozlowski@linaro.org
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Arnd Bergmann [Fri, 14 Apr 2023 13:13:22 +0000 (15:13 +0200)]
Merge tag 'samsung-dt64-6.4' of https://git./linux/kernel/git/krzk/linux into soc/dt
Samsung DTS ARM64 changes for v6.4
1. Exynos850: add headers with AUD, G3D and HSI clock controller clock
IDs. Add G3D (GPU) clock controller node.
2. Exynos5433: fixes for dtbs_check: move MIPI phy to PMU node.
3. Drop old MSHC aliases (while adding proper mmc-ddr-1_8v which was
selected by the driver based on the MSHC alias) and add generic MMC
aliases in each board. The aliases match known numbering in
the schematics.
* tag 'samsung-dt64-6.4' of https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux:
arm64: dts: exynos: add mmc aliases
arm64: dts: exynos: drop mshc aliases
arm64: dts: exynos: Add CMU_G3D node for Exynos850 SoC
arm64: dts: exynos: move MIPI phy to PMU node in Exynos5433
dt-bindings: clock: exynos850: Add AUD and HSI main gate clocks
dt-bindings: clock: exynos850: Add Exynos850 CMU_G3D
Link: https://lore.kernel.org/r/20230405080438.156805-1-krzysztof.kozlowski@linaro.org
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Marek Vasut [Thu, 6 Apr 2023 16:01:15 +0000 (18:01 +0200)]
dt-bindings: arm: Add Data Modul i.MX8M Plus eDM SBC
Add DT compatible for Data Modul i.MX8M Plus eDM SBC board.
This is an evaluation board for various custom display units.
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Marek Vasut <marex@denx.de>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Stefan Wahren [Tue, 4 Apr 2023 08:02:41 +0000 (10:02 +0200)]
dt-bindings: arm: fsl: Add chargebyte Tarragon
This adds the compatibles for the chargebyte Tarragon boards.
Signed-off-by: Stefan Wahren <stefan.wahren@chargebyte.com>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Stefan Wahren [Tue, 4 Apr 2023 08:02:38 +0000 (10:02 +0200)]
dt-bindings: vendor-prefixes: add chargebyte
chargebyte supplies hardware and software products for all
aspects of charging communication.
https://chargebyte.com/
Signed-off-by: Stefan Wahren <stefan.wahren@chargebyte.com>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Cristian Ciocaltea [Tue, 21 Mar 2023 21:56:20 +0000 (23:56 +0200)]
riscv: dts: allwinner: d1: Switch dma-names order for snps,dw-apb-uart nodes
Commit
370f696e4474 ("dt-bindings: serial: snps-dw-apb-uart: add dma &
dma-names properties") documented dma-names property to handle Allwinner
D1 dtbs_check warnings, but relies on the rx->tx ordering, which is the
reverse of what a bunch of different boards expect.
The initial proposed solution was to allow a flexible dma-names order in
the binding, due to potential ABI breakage concerns after fixing the DTS
files. But luckily the Allwinner boards are not affected, since they are
using a shared DMA channel for rx and tx.
Hence, the first step in fixing the inconsistency was to change
dma-names order in the binding to tx->rx.
Do the same for the snps,dw-apb-uart nodes in the DTS file.
Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
Link: https://lore.kernel.org/r/20230321215624.78383-7-cristian.ciocaltea@collabora.com
Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com>
Cristian Ciocaltea [Tue, 21 Mar 2023 21:56:19 +0000 (23:56 +0200)]
ARM: dts: sunxi: h3/h5: Switch dma-names order for snps,dw-apb-uart nodes
Commit
370f696e4474 ("dt-bindings: serial: snps-dw-apb-uart: add dma &
dma-names properties") documented dma-names property to handle Allwinner
D1 dtbs_check warnings, but relies on the rx->tx ordering, which is the
reverse of what a bunch of different boards expect.
The initial proposed solution was to allow a flexible dma-names order in
the binding, due to potential ABI breakage concerns after fixing the DTS
files. But luckily the Allwinner boards are not affected, since they are
using a shared DMA channel for rx and tx.
Hence, the first step in fixing the inconsistency was to change
dma-names order in the binding to tx->rx.
Do the same for the snps,dw-apb-uart nodes in the DTS file.
Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
Acked-by: Jernej Skrabec <jernej.skrabec@gmail.com>
Link: https://lore.kernel.org/r/20230321215624.78383-6-cristian.ciocaltea@collabora.com
Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com>
Cristian Ciocaltea [Tue, 21 Mar 2023 21:56:18 +0000 (23:56 +0200)]
ARM: dts: sun8i: v3s: Switch dma-names order for snps,dw-apb-uart nodes
Commit
370f696e4474 ("dt-bindings: serial: snps-dw-apb-uart: add dma &
dma-names properties") documented dma-names property to handle Allwinner
D1 dtbs_check warnings, but relies on the rx->tx ordering, which is the
reverse of what a bunch of different boards expect.
The initial proposed solution was to allow a flexible dma-names order in
the binding, due to potential ABI breakage concerns after fixing the DTS
files. But luckily the Allwinner boards are not affected, since they are
using a shared DMA channel for rx and tx.
Hence, the first step in fixing the inconsistency was to change
dma-names order in the binding to tx->rx.
Do the same for the snps,dw-apb-uart nodes in the DTS file.
Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
Acked-by: Jernej Skrabec <jernej.skrabec@gmail.com>
Link: https://lore.kernel.org/r/20230321215624.78383-5-cristian.ciocaltea@collabora.com
Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com>
Cristian Ciocaltea [Tue, 21 Mar 2023 21:56:17 +0000 (23:56 +0200)]
ARM: dts: sun8i: a23/a33: Switch dma-names order for snps,dw-apb-uart nodes
Commit
370f696e4474 ("dt-bindings: serial: snps-dw-apb-uart: add dma &
dma-names properties") documented dma-names property to handle Allwinner
D1 dtbs_check warnings, but relies on the rx->tx ordering, which is the
reverse of what a bunch of different boards expect.
The initial proposed solution was to allow a flexible dma-names order in
the binding, due to potential ABI breakage concerns after fixing the DTS
files. But luckily the Allwinner boards are not affected, since they are
using a shared DMA channel for rx and tx.
Hence, the first step in fixing the inconsistency was to change
dma-names order in the binding to tx->rx.
Do the same for the snps,dw-apb-uart nodes in the DTS file.
Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
Acked-by: Jernej Skrabec <jernej.skrabec@gmail.com>
Link: https://lore.kernel.org/r/20230321215624.78383-4-cristian.ciocaltea@collabora.com
Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com>
Cristian Ciocaltea [Tue, 21 Mar 2023 21:56:16 +0000 (23:56 +0200)]
ARM: dts: sun6i: a31: Switch dma-names order for snps,dw-apb-uart nodes
Commit
370f696e4474 ("dt-bindings: serial: snps-dw-apb-uart: add dma &
dma-names properties") documented dma-names property to handle Allwinner
D1 dtbs_check warnings, but relies on the rx->tx ordering, which is the
reverse of what a bunch of different boards expect.
The initial proposed solution was to allow a flexible dma-names order in
the binding, due to potential ABI breakage concerns after fixing the DTS
files. But luckily the Allwinner boards are not affected, since they are
using a shared DMA channel for rx and tx.
Hence, the first step in fixing the inconsistency was to change
dma-names order in the binding to tx->rx.
Do the same for the snps,dw-apb-uart nodes in the DTS file.
Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
Acked-by: Jernej Skrabec <jernej.skrabec@gmail.com>
Link: https://lore.kernel.org/r/20230321215624.78383-3-cristian.ciocaltea@collabora.com
Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com>
Marek Vasut [Thu, 6 Apr 2023 16:01:16 +0000 (18:01 +0200)]
arm64: dts: imx8mp: Add support for Data Modul i.MX8M Plus eDM SBC
Add support for Data Modul i.MX8M Plus eDM SBC board. This is an
evaluation board for various custom display units. Currently
supported are serial console, ethernet, eMMC, SD, SPI NOR,
USB host and USB OTG.
Reviewed-by: Fabio Estevam <festevam@denx.de>
Signed-off-by: Marek Vasut <marex@denx.de>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Roan van Dijk [Thu, 30 Mar 2023 09:16:13 +0000 (11:16 +0200)]
ARM: stm32: add initial documentation for STM32MP151
This patch adds initial documentation of STM32MP151 microprocessor (MPU)
based on Arm Cortex-A7.
Signed-off-by: Roan van Dijk <roan@protonic.nl>
Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
Marek Vasut [Wed, 5 Apr 2023 16:52:14 +0000 (18:52 +0200)]
arm64: dts: imx8mp: Add display pipeline components
Add LCDIF scanout engine and DSIM bridge nodes for i.MX8M Plus.
This makes the DSI display pipeline available on this SoC.
Reviewed-by: Fabio Estevam <festevam@gmail.com>
Signed-off-by: Marek Vasut <marex@denx.de>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Marek Vasut [Wed, 5 Apr 2023 16:52:13 +0000 (18:52 +0200)]
arm64: dts: imx8mn: Add display pipeline components
Add LCDIF scanout engine and DSIM bridge nodes for i.MX8M Nano.
This makes the DSI display pipeline available on this SoC.
Signed-off-by: Marek Vasut <marex@denx.de>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Marek Vasut [Wed, 5 Apr 2023 16:52:12 +0000 (18:52 +0200)]
arm64: dts: imx8mm: Add display pipeline components
Add LCDIF scanout engine and DSIM bridge nodes for i.MX8M Mini.
This makes the DSI display pipeline available on this SoC.
Reviewed-by: Alexander Stein <alexander.stein@ew.tq-group.com>
Reviewed-by: Fabio Estevam <festevam@gmail.com>
Signed-off-by: Marek Vasut <marex@denx.de>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Stefan Wahren [Tue, 4 Apr 2023 08:02:42 +0000 (10:02 +0200)]
ARM: dts: imx6ull: Add chargebyte Tarragon support
This adds the support for chargebyte Tarragon, which is an Electrical
Vehicle Supply Equipment (EVSE) for AC charging stations
(according to IEC 61851, ISO 15118).
The Tarragon board is based on an i.MX6ULL SoC and is available in
4 variants (Master, Slave, SlaveXT, Micro), which provide more or
less peripherals.
Supported features:
* 512 MB DDR RAM
* eMMC
* Debug UART
* 100 Mbit Ethernet
* USB 2.0 Host interface
* Powerline communication (QCA700x)
* 2x RS485
* Digital in- and outputs (12 V)
* One-Wire master for external temp sensors
* 2x relay outputs
* 2x motor interfaces
Link: https://chargebyte.com/products/charging-station-communication/charge-control-c
Signed-off-by: Stefan Wahren <stefan.wahren@chargebyte.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Frank Li [Mon, 27 Mar 2023 14:55:23 +0000 (10:55 -0400)]
arm64: dts: freescale: imx8qxp-mek: enable cadence usb3
Enable USB3 controller, phy and typec related nodes.
Signed-off-by: Frank Li <Frank.Li@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Frank Li [Mon, 27 Mar 2023 14:55:22 +0000 (10:55 -0400)]
arm64: dts: imx8qxp: add cadence usb3 support
There are cadence usb3.0 controller in 8qxp and 8qm.
Add usb3 node at common connect subsystem.
Signed-off-by: Frank Li <Frank.Li@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Peng Fan [Tue, 28 Mar 2023 06:11:23 +0000 (14:11 +0800)]
arm64: dts: imx8mq-librem5: add missing #clock-cells
'#clock-cells' is a dependency of 'clock-output-names', following
binding doc, add it.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Peng Fan [Tue, 28 Mar 2023 03:36:40 +0000 (11:36 +0800)]
arm64: dts: imx8mm-prt8mm: update pinctrl to match dtschema
The dtschema requires 'grp' in the end, so update the name
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Peng Fan [Tue, 28 Mar 2023 03:36:39 +0000 (11:36 +0800)]
arm64: dts: imx8mn-bsh-smm: update pinctrl to match dtschema
The dtschema requires 'grp' in the end, so update the name
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Peng Fan [Tue, 28 Mar 2023 03:36:38 +0000 (11:36 +0800)]
arm64: dts: imx8mm-emcon: update pinctrl to match dtschema
The dtschema requires 'grp' in the end, so update the name
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Peng Fan [Tue, 28 Mar 2023 03:36:37 +0000 (11:36 +0800)]
arm64: dts: imx8mq-librem5: update pinctrl to match dtschema
The dtschema requires 'grp' in the end, so update the name.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Peng Fan [Tue, 28 Mar 2023 03:36:36 +0000 (11:36 +0800)]
arm64: dts: imx8mm-ddr4-evk: update gpmi pinctrl to match dtschema
The dtschema requires 'grp' in the end, so update the name.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Peng Fan [Tue, 28 Mar 2023 03:36:35 +0000 (11:36 +0800)]
arm64: dts: imx8mn-evk: update i2c pinctrl to match dtschema
The dtschema requires 'grp' in the end, so update the name.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Uwe Kleine-König [Mon, 27 Mar 2023 17:35:26 +0000 (19:35 +0200)]
arm64: dts: imx8mp: Add GPT blocks
The i.MX8MP includes the same GPT blocks as the i.MX6DL. Add all 6
instances.
Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Peng Fan [Wed, 22 Mar 2023 05:25:03 +0000 (13:25 +0800)]
arm64: dts: imx8-apalis-v1.1: drop ci-disable-lpm
This is an NXP downstream property. And no binding doc, and no
driver use this property. So drop it
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Conor Dooley [Wed, 5 Apr 2023 21:20:55 +0000 (22:20 +0100)]
Merge branch 'riscv-jh7110_initial_dts' into riscv-dt-for-next
Merge Hal's series adding support for the new StarFive JH7110 SoC.
There's a few bindings here for core components that were not picked up
by the various maintainers for the subsystems (previously Palmer would
pick these up via the RISC-V tree) & the first two commits in the branch
are shared with the clk tree, since the dts depends on defines in the
dt-binding headers.
This is based on -rc2, as the board does not actually boot on -rc1
due to the bug Linus introduced.
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
Emil Renner Berthing [Sat, 1 Apr 2023 11:19:33 +0000 (19:19 +0800)]
riscv: dts: starfive: Add StarFive JH7110 VisionFive 2 board device tree
Add a minimal device tree for StarFive JH7110 VisionFive 2 board
which has version A and version B. Support booting and basic
clock/reset/pinctrl/uart drivers.
Tested-by: Tommaso Merciai <tomm.merciai@gmail.com>
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
Co-developed-by: Jianlong Huang <jianlong.huang@starfivetech.com>
Signed-off-by: Jianlong Huang <jianlong.huang@starfivetech.com>
Co-developed-by: Hal Feng <hal.feng@starfivetech.com>
Signed-off-by: Hal Feng <hal.feng@starfivetech.com>
Reviewed-by: Emil Renner Berthing <emil.renner.berthing@canonical.com>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
Jianlong Huang [Sat, 1 Apr 2023 11:19:32 +0000 (19:19 +0800)]
riscv: dts: starfive: Add StarFive JH7110 pin function definitions
Add pin function definitions for StarFive JH7110 SoC.
Tested-by: Tommaso Merciai <tomm.merciai@gmail.com>
Co-developed-by: Emil Renner Berthing <kernel@esmil.dk>
Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
Signed-off-by: Jianlong Huang <jianlong.huang@starfivetech.com>
Signed-off-by: Hal Feng <hal.feng@starfivetech.com>
Reviewed-by: Emil Renner Berthing <emil.renner.berthing@canonical.com>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
Emil Renner Berthing [Sat, 1 Apr 2023 11:19:31 +0000 (19:19 +0800)]
riscv: dts: starfive: Add initial StarFive JH7110 device tree
Add initial device tree for the JH7110 RISC-V SoC by StarFive
Technology Ltd.
Tested-by: Tommaso Merciai <tomm.merciai@gmail.com>
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
Co-developed-by: Jianlong Huang <jianlong.huang@starfivetech.com>
Signed-off-by: Jianlong Huang <jianlong.huang@starfivetech.com>
Co-developed-by: Hal Feng <hal.feng@starfivetech.com>
Signed-off-by: Hal Feng <hal.feng@starfivetech.com>
[conor: squashed in the removal of the S7's non-existent mmu]
Reviewed-by: Emil Renner Berthing <emil.renner.berthing@canonical.com>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
Hal Feng [Sat, 1 Apr 2023 11:19:30 +0000 (19:19 +0800)]
dt-bindings: riscv: Add SiFive S7 compatible
Add a new compatible string in cpu.yaml for SiFive S7 CPU
core which is used on SiFive U74-MC core complex etc.
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Emil Renner Berthing <emil.renner.berthing@canonical.com>
Signed-off-by: Hal Feng <hal.feng@starfivetech.com>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
Emil Renner Berthing [Sat, 1 Apr 2023 11:19:29 +0000 (19:19 +0800)]
dt-bindings: interrupt-controller: Add StarFive JH7110 plic
Add compatible string for StarFive JH7110 plic.
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Emil Renner Berthing <emil.renner.berthing@canonical.com>
Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
Signed-off-by: Hal Feng <hal.feng@starfivetech.com>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
Emil Renner Berthing [Sat, 1 Apr 2023 11:19:28 +0000 (19:19 +0800)]
dt-bindings: timer: Add StarFive JH7110 clint
Add compatible string for the StarFive JH7110 clint.
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Emil Renner Berthing <emil.renner.berthing@canonical.com>
Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
Signed-off-by: Hal Feng <hal.feng@starfivetech.com>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
Emil Renner Berthing [Sat, 1 Apr 2023 11:19:14 +0000 (19:19 +0800)]
dt-bindings: clock: Add StarFive JH7110 always-on clock and reset generator
Add bindings for the always-on clock and reset generator (AONCRG) on the
JH7110 RISC-V SoC by StarFive Ltd.
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Reviewed-by: Emil Renner Berthing <emil.renner.berthing@canonical.com>
Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
Signed-off-by: Hal Feng <hal.feng@starfivetech.com>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
Emil Renner Berthing [Sat, 1 Apr 2023 11:19:13 +0000 (19:19 +0800)]
dt-bindings: clock: Add StarFive JH7110 system clock and reset generator
Add bindings for the system clock and reset generator (SYSCRG) on the
JH7110 RISC-V SoC by StarFive Ltd.
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Reviewed-by: Emil Renner Berthing <emil.renner.berthing@canonical.com>
Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
Signed-off-by: Hal Feng <hal.feng@starfivetech.com>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
Ben Dooks [Fri, 27 Jan 2023 09:39:10 +0000 (09:39 +0000)]
arm64: tegra: Add vccmq on Jetson TX2
The TX2 SoM's SDIO WiFI card is connected via mmc@
3440000 however it does
not look like the upstream kernel is even bothering to power this (and
the regulator framework shuts down this power rail post kernel init).
The issue seems to be a missing link for vccq from the MAX77620 PMIC's LDO5
which is labeled vddio_sdmmc3 (and not used anywhere else) to the mmc@
3440000
node to ensure there is at leasr bus power.
Note this does not fix the WiFi issue on upstream kernels, there is still
something else missing that gets the BCM WiFi device to detect properly.
Signed-off-by: Ben Dooks <ben.dooks@codethink.co.uk>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Jon Hunter [Tue, 31 Jan 2023 17:57:47 +0000 (17:57 +0000)]
arm64: tegra: Populate USB Type-C Controller for Jetson AGX Orin
Add the USB Type-C controller that is present on the Jetson AGX Orin
board. The ports for the Type-C controller are not populated yet, but
will be added later once the USB host and device support for Jetson AGX
Orin is enabled.
This is based upon a patch from Wayne Chang <waynec@nvidia.com>.
Signed-off-by: Jon Hunter <jonathanh@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Krzysztof Kozlowski [Tue, 7 Feb 2023 19:28:49 +0000 (20:28 +0100)]
dt-bindings: soc: samsung: exynos-pmu: allow phys as child on Exynos3 and Exynos4
Just like on Exynos5250, Exynos5420 and Exynos5433 the MIPI phy is
actually part of the Power Management Unit system controller thus allow
it as PMU's child.
Acked-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/20230207192851.549242-1-krzysztof.kozlowski@linaro.org
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Sameer Pujar [Mon, 13 Feb 2023 04:44:34 +0000 (10:14 +0530)]
arm64: tegra: Audio codec support on Jetson AGX Orin
Jetson AGX Orin has onboard RT5640 audio codec. This patch adds the
codec device node and the bindings to I2S1 interface.
Signed-off-by: Sameer Pujar <spujar@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Arnd Bergmann [Tue, 4 Apr 2023 14:28:16 +0000 (16:28 +0200)]
Merge tag 'amlogic-arm64-dt-for-v6.4' of https://git./linux/kernel/git/amlogic/linux into soc/dt
Amlogic ARM64 DT changes for v6.4:
- set of DT bindings check fixes
- adjust order of some compatibles to match dt-schema migration
- add support for BananaPi M2S variants
- gxbb-kii-pro: add audio & bluetooth support
- meson-a1: add gpio_intc node
- gxl: use gxl mdio multiplexer
- Add initial support for BPI-CM4 module with BPI-CM4IO baseboard
* tag 'amlogic-arm64-dt-for-v6.4' of https://git.kernel.org/pub/scm/linux/kernel/git/amlogic/linux:
arm64: dts: amlogic: Add initial support for BPI-CM4 module with BPI-CM4IO baseboard
dt-bindings: arm: amlogic: Document the boards with the BPI-CM4 connected
arm64: dts: amlogic: gxl: use gxl mdio multiplexer
arm64: dts: meson-a1: add gpio_intc node
arm64: dts: meson: gxbb-kii-pro: add initial audio support
arm64: dts: meson: gxbb-kii-pro: complete the bluetooth node
arm64: dts: meson: gxbb-kii-pro: sort and tidy the dts
arm64: dts: meson: adjust order of some compatibles
arm64: dts: meson: add support for BananaPi M2S variants
dt-bindings: arm: amlogic: add support for BananaPi M2S variants
arm64: dts: amlogic: meson-gxm-s912-libretech-pc: remove unused pinctrl-names from phy node
arm64: dts: amlogic: meson-sm1: use correct enable-gpios
arm64: dts: amlogic: meson-s4: fix apb4 bus node name
arm64: dts: amlogic: meson-g12b-odroid-go-ultra: rename keypad-gpio pinctrl node
arm64: dts: amlogic: meson-g12b-radxa-zero2: fix pwm clock names
arm64: dts: amlogic: meson-axg-jethome-jethub-j1xx: remove invalid #gpio-cells in onewire node
arm64: dts: amlogic: meson-gxm-s912-libretech-pc: add simple connector node in fusb302 node
arm64: dts: amlogic: meson-sm1-bananapi: correct usb-hub hog node name
Link: https://lore.kernel.org/r/1b955bb7-1a35-8d67-beb6-dd289533ff6f@linaro.org
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Arnd Bergmann [Tue, 4 Apr 2023 14:27:38 +0000 (16:27 +0200)]
Merge tag 'amlogic-arm-dt-for-v6.4' of https://git./linux/kernel/git/amlogic/linux into soc/dt
Amlogic ARM DT changes for v6.4:
- adjust order of some compatibles
- meson8: add the xtal_32k_out pin
- meson8: add the SDXC_A pins
- mxiii-plus: Enable Bluetooth and WiFi support
* tag 'amlogic-arm-dt-for-v6.4' of https://git.kernel.org/pub/scm/linux/kernel/git/amlogic/linux:
ARM: dts: meson8m2: mxiii-plus: Enable Bluetooth and WiFi support
ARM: dts: meson8: add the SDXC_A pins
ARM: dts: meson8: add the xtal_32k_out pin
arm: dts: meson: adjust order of some compatibles
Link: https://lore.kernel.org/r/eb1f32f8-822d-9cfc-fca6-9e044bf4a5ab@linaro.org
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Neil Armstrong [Mon, 3 Apr 2023 07:42:21 +0000 (09:42 +0200)]
dt-bindings: arm: oxnas: remove obsolete bindings
Due to lack of maintainance and stall of development for a few years now,
and since no new features will ever be added upstream, remove the
OX810 and OX820 SoC and boards bindings.
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Acked-by: Arnd Bergmann <arnd@arndb.de>
Acked-by: Daniel Golle <daniel@makrotopia.org>
Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Neil Armstrong [Mon, 3 Apr 2023 07:42:18 +0000 (09:42 +0200)]
ARM: dts: oxnas: remove obsolete device tree files
Due to lack of maintainance and stall of development for a few years now,
and since no new features will ever be added upstream, remove support
for OX810 and OX820 devices.
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Acked-by: Arnd Bergmann <arnd@arndb.de>
Acked-by: Daniel Golle <daniel@makrotopia.org>
Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Arnd Bergmann [Tue, 4 Apr 2023 14:24:46 +0000 (16:24 +0200)]
Merge tag 'at91-dt-6.4' of git://git./linux/kernel/git/at91/linux into soc/dt
AT91 device tree updates for 6.4:
It contains:
- Update to maximum frequency for QSPI on several boards thanks
to the additon of the new spi-cs-setup-ns property.
* tag 'at91-dt-6.4' of git://git.kernel.org/pub/scm/linux/kernel/git/at91/linux:
ARM: dts: at91: sam9x60ek: Set sst26vf064b SPI NOR flash at its maximum frequency
ARM: dts: at91: sama5d2_icp: Set sst26vf064b SPI NOR flash at its maximum frequency
ARM: dts: at91-sama5d27_som1: Set sst26vf064b SPI NOR flash at its maximum frequency
ARM: dts: at91-sama5d27_wlsom1: Set sst26vf064b SPI NOR flash at its maximum frequency
Link: https://lore.kernel.org/r/20230331142751.41522-1-nicolas.ferre@microchip.com
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Arnd Bergmann [Tue, 4 Apr 2023 14:20:32 +0000 (16:20 +0200)]
Merge tag 'omap-for-v6.4/dt-overlays-signed' of git://git./linux/kernel/git/tmlind/linux-omap into soc/dt
Devicetree overlays for omaps for v6.4
Devicetree overlays for omaps to enable the optional LCD and touchscreen
modules on am57xx-evm and am57xx-idk boards.
* tag 'omap-for-v6.4/dt-overlays-signed' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap:
ARM: dts: am57xx-idk: Add IDK displays and touchscreens
ARM: dts: ti: Add AM57xx GP EVM Rev A3 board support
ARM: dts: ti: Add AM57xx GP EVM board support
Link: https://lore.kernel.org/r/pull-1680180448-508978@atomide.com
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Arnd Bergmann [Tue, 4 Apr 2023 14:19:30 +0000 (16:19 +0200)]
Merge tag 'omap-for-v6.4/dt-signed' of git://git./linux/kernel/git/tmlind/linux-omap into soc/dt
Devicetree changes for omaps for v6.4
Devicetree changes for omaps for gta04, Phytec am335x devices, and to
drop a obsolete compatible property:
- A non-urgent fix for gta04 to enable more dma channels for some audio
configurations
- Update the dts compatible and vendor prefixes for gta04
- A series of updates for Phytec am335x based boards to configure more
devices like rtc and audio, and a few clean-up patches
- A change to drop the usage of "ti,omap36xx" compatible, the driver
code already checks for "ti,omap3630" that is also alread set in the
dts files. This makes the yaml binding conversion a bit simpler.
* tag 'omap-for-v6.4/dt-signed' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap:
ARM: dts: omap: Drop ti,omap36xx compatible
ARM: dts: am335x-phycore-som: Remove superseded/invalid GPMC NAND type.
ARM: dts: am335x-pcm-953: Remove superseded/invalid LED trigger.
ARM: dts: am335x-phycore-som: Remove underscore in node names.
ARM: dts: am335x-regor: Remove underscore in node names.
ARM: dts: am335x-pcm-935: Remove underscore in node names.
ARM: dts: am335x-wega: Change node name of sound card, remove underscores.
ARM: dts: am335x-wega: Fix audio codec by using simple-audio-card driver.
ARM: dts: am335x-phycore-som: Add alias for TPS65910 RTC
ARM: dts: omap3-gta04: fix compatible record for GTA04 board
ARM: dts: gta04: fix excess dma channel usage
Link: https://lore.kernel.org/r/pull-1680180389-756753@atomide.com
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Arnd Bergmann [Tue, 4 Apr 2023 14:17:15 +0000 (16:17 +0200)]
Merge tag 'renesas-dts-for-v6.4-tag1' of git://git./linux/kernel/git/geert/renesas-devel into soc/dt
Renesas DTS updates for v6.4
- Add USB3 support for the RZ/V2M SoC and the RZ/V2M Evaluation Kit 2.0,
- Add uSD card and eMMC support for the RZ/V2M Evaluation Kit 2.0,
- Add CAN-FD, thermal, GMSL2 video capture, and sound support for the
R-Car V4H SoC and the White-Hawk development board,
- Add PMU support for the RZ/G2UL, RZ/G2L{,C}, and RZ/V2L SoCs,
- Drop support for the obsolete R-Car H3 ES1.* (R8A77950) SoC,
- Add I2C EEPROM support for the Atmark Techno Armadillo-800-EVA, and
the Renesas Condor and ULCB development boards,
- Miscellaneous fixes and improvements.
* tag 'renesas-dts-for-v6.4-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel: (30 commits)
arm64: dts: renesas: r8a779a0: Update CAN-FD to R-Car Gen4 compatible value
arm64: dts: renesas: ulcb: Add I2C EEPROM for PMIC
arm64: dts: renesas: condor: Add I2C EEPROM for PMIC
ARM: dts: armadillo800eva: Add I2C EEPROM for MAC address
arm64: dts: renesas: Remove R-Car H3 ES1.* devicetrees
arm64: dts: renesas: white-hawk: Add R-Car Sound support
arm64: dts: renesas: r8a779g0: R-Car Sound support
arm64: dts: renesas: r9a07g043: Update IRQ numbers for SSI channels
arm64: dts: renesas: r9a07g054: Update IRQ numbers for SSI channels
arm64: dts: renesas: r9a07g044: Update IRQ numbers for SSI channels
arm64: dts: renesas: r8a774c0: Remove bogus voltages from OPP table
arm64: dts: renesas: r8a77990: Remove bogus voltages from OPP table
arm64: dts: renesas: r9a07g054: Add Cortex-A55 PMU node
arm64: dts: renesas: white-hawk-csi-dsi: Add and connect MAX96712
arm64: dts: renesas: r8a779g0: Add and connect all CSI-2, ISP and VIN nodes
arm64: dts: renesas: r8a779f0: Use proper labels for thermal zones
arm64: dts: renesas: r8a779g0: Add thermal nodes
arm64: dts: renesas: rzv2mevk2: Add uart0 pins
arm64: dts: renesas: Drop specifying the GIC_CPU_MASK_SIMPLE() for GICv3 systems
arm64: dts: renesas: r9a07g044: Add Cortex-A55 PMU node
...
Link: https://lore.kernel.org/r/cover.1679907064.git.geert+renesas@glider.be
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Arnd Bergmann [Tue, 4 Apr 2023 14:16:18 +0000 (16:16 +0200)]
Merge tag 'renesas-dt-bindings-for-v6.4-tag1' of git://git./linux/kernel/git/geert/renesas-devel into soc/dt
Renesas DT binding updates for v6.4
- Document support for the Renesas RZ/N1 EB board with an RZ/N1D-DB
daughter board,
- Drop support for the obsolete R-Car H3 ES1.* (R8A77950) SoC.
* tag 'renesas-dt-bindings-for-v6.4-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel:
dt-bindings: soc: renesas: Remove R-Car H3 ES1.*
dt-bindings: soc: renesas: renesas.yaml: Add renesas,rzn1d400-eb compatible
Link: https://lore.kernel.org/r/cover.1679907062.git.geert+renesas@glider.be
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Rob Herring [Fri, 31 Mar 2023 18:21:59 +0000 (13:21 -0500)]
dt-bindings: arm: nvidia: Drop unneeded quotes
Cleanup bindings dropping unneeded quotes. Once all these are fixed,
checking for this can be enabled in yamllint.
Signed-off-by: Rob Herring <robh@kernel.org>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Maxim Schwalm [Wed, 29 Mar 2023 09:04:01 +0000 (12:04 +0300)]
ARM: tegra30: Use cpu* labels
Replace cpu paths with labels since those already exist in tree.
Signed-off-by: Maxim Schwalm <maxim.schwalm@gmail.com>
Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Svyatoslav Ryhel [Wed, 29 Mar 2023 09:04:03 +0000 (12:04 +0300)]
ARM: tegra30: peripherals: Add 266.5MHz nodes
LG Optimus Vu (p895) and Optimus 4X HD (p880) have 266.5MHz RAM
clock and require this entry to work with it correctly.
Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Svyatoslav Ryhel [Wed, 29 Mar 2023 09:04:02 +0000 (12:04 +0300)]
ARM: tegra: asus-tf101: Fix accelerometer mount matrix
Accelerometer mount matrix used in tf101 downstream is inverted.
This new matrix was generated on actual device using calibration
script, like on other transformers.
Tested-by: Robert Eckelmann <longnoserob@gmail.com>
Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Thierry Reding [Fri, 31 Mar 2023 16:29:14 +0000 (18:29 +0200)]
arm64: tegra: Support Jetson Orin NX reference platform
Add support for the combination of the NVIDIA Jetson Orin NX (P3767, SKU
0) module and the P3768 carrier board.
Signed-off-by: Thierry Reding <treding@nvidia.com>
Thierry Reding [Fri, 31 Mar 2023 16:29:13 +0000 (18:29 +0200)]
arm64: tegra: Support Jetson Orin NX
This adds a device tree for the Jetson Orin NX module, which is Jetson
AGX Orin's little sibling with 6 or 8 ARM Cortex-A78AE cores, an Ampere
GPU (1024 GPU and 32 tensor cores) and a number of accelerators for
machine learning, image processing and more.
The Jetson Orin NX comes with either 8 or 16 GiB of 128-bit LPDDR5 and
supports NVME for mass storage.
Signed-off-by: Thierry Reding <treding@nvidia.com>
Thierry Reding [Fri, 31 Mar 2023 16:29:12 +0000 (18:29 +0200)]
dt-bindings: tegra: Document Jetson Orin NX reference platform
Document the combination of the P3768 carrier board with the P3767
(Jetson Orin NX) module.
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Thierry Reding [Fri, 31 Mar 2023 16:29:11 +0000 (18:29 +0200)]
dt-bindings: tegra: Document Jetson Orin NX
The Jetson Orin NX is the latest iteration in the NX family of Jetson
products. Document the compatible strings used for these devices.
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Henrik Grimler [Sun, 2 Apr 2023 14:47:24 +0000 (16:47 +0200)]
ARM: dts: exynos: add mmc aliases
Add aliases for eMMC, SD card and WiFi where applicable, so that
assigned mmc indeces are always the same.
Co-developed-by: Anton Bambura <jenneron@protonmail.com>
Signed-off-by: Anton Bambura <jenneron@protonmail.com>
[ Tested on exynos5800-peach-pi ]
Tested-by: Valentine Iourine <iourine@iourine.msk.su>
Signed-off-by: Henrik Grimler <henrik@grimler.se>
Tested-by: Marek Szyprowski <m.szyprowski@samsung.com>
Link: https://lore.kernel.org/r/20230402144724.17839-3-henrik@grimler.se
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Henrik Grimler [Sun, 2 Apr 2023 14:47:23 +0000 (16:47 +0200)]
ARM: dts: exynos: replace mshc0 alias with mmc-ddr-1_8v property
Previously, the mshc0 alias has been necessary so that
MMC_CAP_1_8V_DDR | MMC_CAP_8_BIT_DATA are set for mshc_0/mmc_0.
However, these capabilities should be described in the device tree so
that we do not have to rely on the alias.
The property mmc-ddr-1_8v replaces MMC_CAP_1_8V_DDR, while bus_width =
<8>, which is already set for all the mshc0/mmc0 nodes, replaces
MMC_CAP_8_BIT_DATA.
Also drop other mshc aliases as they are not needed.
Signed-off-by: Henrik Grimler <henrik@grimler.se>
Tested-by: Marek Szyprowski <m.szyprowski@samsung.com>
Link: https://lore.kernel.org/r/20230402144724.17839-2-henrik@grimler.se
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Jon Hunter [Mon, 6 Mar 2023 15:01:57 +0000 (15:01 +0000)]
arm64: tegra: Add DSU PMUs for Tegra234
Populate the DynamIQ Shared Unit (DSU) Performance Monitor Unit (PMU)
devices for Tegra234 which has one DSU PMU per CPU cluster.
Signed-off-by: Jon Hunter <jonathanh@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Krzysztof Kozlowski [Mon, 23 Jan 2023 15:15:43 +0000 (16:15 +0100)]
arm64: tegra: Drop serial clock-names and reset-names
The serial node does not use clock-names and reset-names:
tegra234-sim-vdk.dtb: serial@
3100000: Unevaluated properties are not allowed ('clock-names', 'reset-names' were unexpected)
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Patrice Chotard [Fri, 31 Mar 2023 07:19:07 +0000 (09:19 +0200)]
ARM: dts: stm32: Add QSPI support on STM32MP13x SoC family
Add QSPI support on STM32MP13x SoC family
Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com>
Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
Christophe Kerello [Tue, 28 Mar 2023 17:07:11 +0000 (19:07 +0200)]
ARM: dts: stm32: add FMC support on STM32MP13x SoC family
Add FMC support on STM32MP13x SoC family.
Signed-off-by: Christophe Kerello <christophe.kerello@foss.st.com>
Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
Pierre-Yves MORDRET [Mon, 3 Apr 2023 08:01:06 +0000 (10:01 +0200)]
ARM: dts: stm32: YAML validation fails for Argon Boards
"make dtbs_check" gives following output :
stm32mp157c-emstamp-argon.dtb: gpu@
59000000: 'contiguous-area' does not match
any of the regexes: 'pinctrl-[0-9]+'
From schema: Documentation/devicetree/bindings/gpu/vivante,gc.yaml
Signed-off-by: Pierre-Yves MORDRET <pierre-yves.mordret@foss.st.com>
Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
Pierre-Yves MORDRET [Mon, 3 Apr 2023 07:58:31 +0000 (09:58 +0200)]
ARM: dts: stm32: YAML validation fails for Odyssey Boards
"make dtbs_check" gives following output :
stm32mp157c-odyssey.dt.yaml: gpu@
59000000: 'contiguous-area' does not match
any of the regexes: 'pinctrl-[0-9]+'
From schema: Documentation/devicetree/bindings/gpu/vivante,gc.yaml
Signed-off-by: Pierre-Yves MORDRET <pierre-yves.mordret@foss.st.com>
Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
Pierre-Yves MORDRET [Mon, 3 Apr 2023 07:54:15 +0000 (09:54 +0200)]
ARM: dts: stm32: YAML validation fails for STM32MP15 ST Boards
"make dtbs_check" gives following output :
stm32mp157x-xxx.dt.yaml: gpu@
59000000: 'contiguous-area' does not match
any of the regexes: 'pinctrl-[0-9]+'
From schema: Documentation/devicetree/bindings/gpu/vivante,gc.yaml
Solve this trouble for STM32MPU Boards :
- stm32mp157c-ed1
- stm32mp157x-dkx
Signed-off-by: Pierre-Yves MORDRET <pierre-yves.mordret@foss.st.com>
Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
Tudor Ambarus [Tue, 28 Mar 2023 10:15:17 +0000 (10:15 +0000)]
ARM: dts: at91: sam9x60ek: Set sst26vf064b SPI NOR flash at its maximum frequency
sam9x60ek populates an sst26vf064b SPI NOR flash. Its maximum operating
frequency for 2.7-3.6V is 104 MHz. As the flash is operated at 3.3V,
increase its maximum supported frequency to 104MHz. The increasing of the
spi-max-frequency value requires the setting of the
"CE# Not Active Hold Time", thus set the spi-cs-setup-ns to a value of 7.
The sst26vf064b datasheet specifies just a minimum value for the
"CE# Not Active Hold Time" and it advertises it to 5 ns. There's no
maximum time specified. I determined experimentally that 5 ns for the
spi-cs-setup-ns is not enough when the flash is operated close to its
maximum frequency and tests showed that 7 ns is just fine, so set the
spi-cs-setup-ns dt property to 7.
With the increase of frequency the reads are now faster with ~33%.
Signed-off-by: Tudor Ambarus <tudor.ambarus@linaro.org>
Link: https://lore.kernel.org/r/20230328101517.1595738-5-tudor.ambarus@linaro.org
Signed-off-by: Nicolas Ferre <nicolas.ferre@microchip.com>
Tudor Ambarus [Tue, 28 Mar 2023 10:15:16 +0000 (10:15 +0000)]
ARM: dts: at91: sama5d2_icp: Set sst26vf064b SPI NOR flash at its maximum frequency
sama5d2_icp populates an sst26vf064b SPI NOR flash. Its maximum operating
frequency for 2.7-3.6V is 104 MHz. As the flash is operated at 3.3V,
increase its maximum supported frequency to 104MHz. The increasing of the
spi-max-frequency value requires the setting of the
"CE# Not Active Hold Time", thus set the spi-cs-setup-ns to a value of 7.
The sst26vf064b datasheet specifies just a minimum value for the
"CE# Not Active Hold Time" and it advertises it to 5 ns. There's no
maximum time specified. I determined experimentally that 5 ns for the
spi-cs-setup-ns is not enough when the flash is operated close to its
maximum frequency and tests showed that 7 ns is just fine, so set the
spi-cs-setup-ns dt property to 7.
With the increase of frequency the reads are now faster with ~37%.
Signed-off-by: Tudor Ambarus <tudor.ambarus@linaro.org>
Tested-by: Nicolas Ferre <nicolas.ferre@microchip.com> # on sama5d2 ICP
Link: https://lore.kernel.org/r/20230328101517.1595738-4-tudor.ambarus@linaro.org
Signed-off-by: Nicolas Ferre <nicolas.ferre@microchip.com>
Tudor Ambarus [Tue, 28 Mar 2023 10:15:15 +0000 (10:15 +0000)]
ARM: dts: at91-sama5d27_som1: Set sst26vf064b SPI NOR flash at its maximum frequency
sama5d27-som1 populates an sst26vf064b SPI NOR flash. Its maximum
operating frequency for 2.7-3.6V is 104 MHz. As the flash is operated
at 3.3V, increase its maximum supported frequency to 104MHz. The
increasing of the spi-max-frequency value requires the setting of the
"CE# Not Active Hold Time", thus set the spi-cs-setup-ns to a value of 7.
The sst26vf064b datasheet specifies just a minimum value for the
"CE# Not Active Hold Time" and it advertises it to 5 ns. There's no
maximum time specified. I determined experimentally that 5 ns for the
spi-cs-setup-ns is not enough when the flash is operated close to its
maximum frequency and tests showed that 7 ns is just fine, so set the
spi-cs-setup-ns dt property to 7.
With the increase of frequency the reads are now faster with ~37%.
Signed-off-by: Tudor Ambarus <tudor.ambarus@linaro.org>
Link: https://lore.kernel.org/r/20230328101517.1595738-3-tudor.ambarus@linaro.org
Signed-off-by: Nicolas Ferre <nicolas.ferre@microchip.com>
Tudor Ambarus [Tue, 28 Mar 2023 10:15:14 +0000 (10:15 +0000)]
ARM: dts: at91-sama5d27_wlsom1: Set sst26vf064b SPI NOR flash at its maximum frequency
sama5d27-wlsom1 populates an sst26vf064b SPI NOR flash. Its maximum
operating frequency for 2.7-3.6V is 104 MHz. As the flash is operated
at 3.3V, increase its maximum supported frequency to 104MHz. The
increasing of the spi-max-frequency value requires the setting of the
"CE# Not Active Hold Time", thus set the spi-cs-setup-ns to a value of 7.
The sst26vf064b datasheet specifies just a minimum value for the
"CE# Not Active Hold Time" and it advertises it to 5 ns. There's no
maximum time specified. I determined experimentally that 5 ns for the
spi-cs-setup-ns is not enough when the flash is operated close to its
maximum frequency and tests showed that 7 ns is just fine, so set the
spi-cs-setup-ns dt property to 7.
With the increase of frequency the reads are now faster with ~37%.
Signed-off-by: Tudor Ambarus <tudor.ambarus@linaro.org>
Link: https://lore.kernel.org/r/20230328101517.1595738-2-tudor.ambarus@linaro.org
Signed-off-by: Nicolas Ferre <nicolas.ferre@microchip.com>
Valentin Caron [Tue, 28 Mar 2023 15:37:23 +0000 (17:37 +0200)]
ARM: dts: stm32: add uart nodes and uart aliases on stm32mp135f-dk
Update device-tree stm32mp135f-dk.dts to add usart1, uart8, usart2
and uart aliases.
- Usart2 is used to interface a BT device, enable it by default.
- Usart1 and uart8 are available on expansion connector.
They are kept disabled. So, the pins are kept in analog state to
lower power consumption by default or can be used as GPIO.
- Uart4 is used for console.
Signed-off-by: Valentin Caron <valentin.caron@foss.st.com>
Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
Valentin Caron [Tue, 28 Mar 2023 15:37:22 +0000 (17:37 +0200)]
ARM: dts: stm32: add pins for usart2/1/4/8 in stm32mp13-pinctrl
Add pins for uart4, uart8, usart1 and usart2 in stm32mp13-pinctrl.dtsi
Theses pins have three states: default, sleep and idle.
Signed-off-by: Valentin Caron <valentin.caron@foss.st.com>
Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
Valentin Caron [Tue, 28 Mar 2023 15:37:21 +0000 (17:37 +0200)]
ARM: dts: stm32: add uart nodes on stm32mp13
Update device-tree stm32mp131.dtsi to add some uart features.
On uart 1, 2, 3, 5, 6, 7, 8 nodes, add compabible, exti interrupts, clock,
reset properties, dma config.
On uart 4 node, only add dma configuration and use exti interrupt.
Signed-off-by: Valentin Caron <valentin.caron@foss.st.com>
Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
Valentin Caron [Tue, 28 Mar 2023 15:37:20 +0000 (17:37 +0200)]
ARM: dts: stm32: clean uart aliases on stm32mp15xx-exx boards
Remove duplicates and clean uart aliases.
Uart aliases and uart pins should be declared and associated to
uart instance at the same time.
Put also aliases node above chosen node as same as stm32mp157c-dk2.dts.
Signed-off-by: Valentin Caron <valentin.caron@foss.st.com>
Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
Valentin Caron [Tue, 28 Mar 2023 15:37:19 +0000 (17:37 +0200)]
ARM: dts: stm32: clean uart aliases on stm32mp15xx-dkx boards
Remove duplicates and clean uart aliases.
Uart aliases and uart pins should be declared and associated to
uart instance at the same time.
Signed-off-by: Valentin Caron <valentin.caron@foss.st.com>
Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
Valentin Caron [Tue, 28 Mar 2023 15:37:18 +0000 (17:37 +0200)]
ARM: dts: stm32: fix slew-rate of USART2 on stm32mp15xx-dkx
On stm32mp15xx-dkx boards:
- Fix slew-rate of USART 2 to 0 like other USARTs, because frequency of
USART pins doesn't exceed 10Mhz.
Signed-off-by: Valentin Caron <valentin.caron@foss.st.com>
Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
Roan van Dijk [Tue, 28 Mar 2023 09:33:11 +0000 (11:33 +0200)]
ARM: stm32: add support for STM32MP151
This patch adds initial support of STM32MP151 microprocessor (MPU)
based on Arm Cortex-A7. New Cortex-A infrastructure (gic, timer,...)
are selected if ARCH_MULTI_V7 is defined.
Signed-off-by: David Jander <david@protonic.nl>
Signed-off-by: Roan van Dijk <roan@protonic.nl>
Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
Svyatoslav Ryhel [Mon, 27 Mar 2023 15:02:19 +0000 (18:02 +0300)]
ARM: tegra: transformers: Bind RT5631 sound nodes
TF201, TF300TG and TF700T support RT5631 codec.
Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Svyatoslav Ryhel [Mon, 27 Mar 2023 15:02:18 +0000 (18:02 +0300)]
ARM: tegra: transformers: Update WM8903 sound nodes
Fix headset detection and use device GPIO microphone detection on WM8903
Transformers.
Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Janne Grunau [Tue, 14 Feb 2023 14:07:23 +0000 (15:07 +0100)]
arm64: dts: apple: t600x: Disable unused PCIe ports
The PCIe ports are unused (without devices) so disable them instead of
removing them.
Signed-off-by: Janne Grunau <j@jannau.net>
Reviewed-by: Sven Peter <sven@svenpeter.dev>
Signed-off-by: Hector Martin <marcan@marcan.st>
Janne Grunau [Tue, 14 Feb 2023 14:07:22 +0000 (15:07 +0100)]
arm64: dts: apple: t8103: Disable unused PCIe ports
The PCIe ports are unused (without devices) so disable them instead of
removing them.
Fixes:
7c77ab91b33d ("arm64: dts: apple: Add missing M1 (t8103) devices")
Signed-off-by: Janne Grunau <j@jannau.net>
Reviewed-by: Sven Peter <sven@svenpeter.dev>
Signed-off-by: Hector Martin <marcan@marcan.st>
Hector Martin [Tue, 7 Mar 2023 12:10:21 +0000 (13:10 +0100)]
arm64: dts: apple: t8112: Initial t8112 (M2) device trees
This adds device trees for the following devices:
- Macbook Air (M2, 2022)
- Macbook Pro 13" (M2, 2022)
- Mac mini (M2, 2023)
This brings the hardware support of the machines to the same level as M1
and M1 Pro / Max / Ultra. Supported hardware include NVMe, PCIe, serial,
pinctrl/gpio, I2C, iommu, watchdog, admac, nco, cpufreq, boot
framebuffer for laptop panels and the interrupt controller.
The ethernet LAN device on the M2 Mac mini is the only working PCIe
device. The Wlan/BT devices are powered off and controlled by the not
yet supported SMC. The ASMedia xHCI on the M2 Mac mini requires firmware
to be loaded at startup.
The main missing hardware support to make these devices useful are the
integrated USB 2/3/4 controller, keyboard and trackpad on the laptops
and SMC to power the PCIe Wlan/BT device on.
The M2 Mac mini has currently no working display output. Due to changes
in the display pipeline it is currently not possible to initialize the
HDMI output in the bootloader.
Co-developed-by: Janne Grunau <j@jannau.net>
Signed-off-by: Janne Grunau <j@jannau.net>
Reviewed-by: Sven Peter <sven@svenpeter.dev>
Signed-off-by: Hector Martin <marcan@marcan.st>
Janne Grunau [Tue, 7 Mar 2023 12:10:20 +0000 (13:10 +0100)]
dt-bindings: arm: apple: Add t8112 j413/j473/j493 compatibles
This adds the following apple,t8112 platforms:
- apple,j413 - MacBook Air (M2, 2022)
- apple,j473 - Mac mini (M2, 2023)
- apple,j493 - MacBook Pro (13-inch, M2, 2022)
The sort order logic here is having SoC numeric code families in release
order, and SoCs within each family in release order:
- t8xxx (Apple HxxP/G series, "phone"/"tablet" chips)
- t8103 (Apple H13G/M1)
- t8112 (Apple H14G/M2)
- t6xxx (Apple HxxJ series, "desktop" chips)
- t6000 (Apple H13J(S)/M1 Pro)
- t6001 (Apple H13J(C)/M1 Max)
- t6002 (Apple H13J(D)/M1 Ultra)
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Janne Grunau <j@jannau.net>
Signed-off-by: Hector Martin <marcan@marcan.st>
Janne Grunau [Tue, 7 Mar 2023 12:10:18 +0000 (13:10 +0100)]
dt-bindings: clock: apple,nco: Add t8112-nco compatible
The block found on Apple's M2 SoC is compatible with the existing driver
so add its per-SoC compatible.
Acked-by: Martin Povišer <povik+lin@cutebit.org>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Janne Grunau <j@jannau.net>
Signed-off-by: Hector Martin <marcan@marcan.st>
Janne Grunau [Tue, 7 Mar 2023 12:10:17 +0000 (13:10 +0100)]
dt-bindings: i2c: apple,i2c: Add apple,t8112-i2c compatible
This block on the Apple M2 is compatible with the existing driver so
just add the per-SoC compatible.
Acked-by: Wolfram Sang <wsa@kernel.org> # for I2C
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Janne Grunau <j@jannau.net>
Signed-off-by: Hector Martin <marcan@marcan.st>
Janne Grunau [Tue, 7 Mar 2023 12:10:16 +0000 (13:10 +0100)]
dt-bindings: pinctrl: apple,pinctrl: Add apple,t8112-pinctrl compatible
This new SoC uses the same pinctrl hardware, so just add a new per-SoC
compatible.
Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Janne Grunau <j@jannau.net>
Signed-off-by: Hector Martin <marcan@marcan.st>
Janne Grunau [Tue, 7 Mar 2023 12:10:15 +0000 (13:10 +0100)]
dt-bindings: pci: apple,pcie: Add t8112 support
The block found in the Apple M2 SoC is compatible with the existing
driver, and supports 4 downstream ports like the t6000 one.
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Janne Grunau <j@jannau.net>
Signed-off-by: Hector Martin <marcan@marcan.st>
Janne Grunau [Tue, 7 Mar 2023 12:10:14 +0000 (13:10 +0100)]
dt-bindings: nvme: apple: Add apple,t8112-nvme-ans2 compatible string
"apple,t8112-nvme-ans2" as found on Apple M2 SoCs is compatible with the
existing driver. Add its SoC specific compatible string to allow special
handling if it'll be necessary.
t8112 uses only 2 power-domains as no 4 and 8 TB configurations are
offered.
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Janne Grunau <j@jannau.net>
Signed-off-by: Hector Martin <marcan@marcan.st>
Janne Grunau [Tue, 7 Mar 2023 12:10:13 +0000 (13:10 +0100)]
dt-bindings: mailbox: apple,mailbox: Add t8112 compatibles
The mailbox hardware remains unchanged on M2 SoCs so just add its
per-SoC compatible.
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Janne Grunau <j@jannau.net>
Signed-off-by: Hector Martin <marcan@marcan.st>
Janne Grunau [Tue, 7 Mar 2023 12:10:12 +0000 (13:10 +0100)]
dt-bindings: iommu: apple,sart: Add apple,t8112-sart compatible string
"apple,t8112-sart" as found on the Apple M2 SoC appears to be SART3 as
well. To allow for later discovered incompatibilities use
'"apple,t8112-sart", "apple,t6000-sart"' as compatible string.
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Janne Grunau <j@jannau.net>
Signed-off-by: Hector Martin <marcan@marcan.st>