linux-2.6-microblaze.git
2 years agodrm/amdgpu/mes: extend mes framework to support multiple mes pipes
Jack Xiao [Wed, 14 Apr 2021 10:00:13 +0000 (18:00 +0800)]
drm/amdgpu/mes: extend mes framework to support multiple mes pipes

Add support for multiple mes pipes, so that reuse the existing
code to initialize more mes pipe and queue.

Signed-off-by: Jack Xiao <Jack.Xiao@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2 years agodrm/amdgpu: allocate doorbell index for mes kiq
Jack Xiao [Wed, 14 Apr 2021 08:22:43 +0000 (16:22 +0800)]
drm/amdgpu: allocate doorbell index for mes kiq

Allocate a doorbell index for mes kiq queue.

Signed-off-by: Jack Xiao <Jack.Xiao@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2 years agodrm/amdgpu: add mes_kiq module parameter v2
Jack Xiao [Wed, 14 Apr 2021 08:04:31 +0000 (16:04 +0800)]
drm/amdgpu: add mes_kiq module parameter v2

mes_kiq parameter is used to enable mes kiq pipe.
This module parameter is unneccessary or enabled by default
in final version.

v2: reword commit message.

Signed-off-by: Jack Xiao <Jack.Xiao@amd.com>
Acked-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2 years agodrm/amdgpu: update mes process/gang/queue definitions
Jack Xiao [Fri, 27 Mar 2020 05:15:56 +0000 (13:15 +0800)]
drm/amdgpu: update mes process/gang/queue definitions

Update the definitions of MES process/gang/queue.

v2: add missing includes
v3: rebase fix, include mm.h

Signed-off-by: Jack Xiao <Jack.Xiao@amd.com>
Acked-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2 years agodrm/amdgpu: use the whole doorbell space for mes
Jack Xiao [Fri, 20 Mar 2020 06:53:07 +0000 (14:53 +0800)]
drm/amdgpu: use the whole doorbell space for mes

Use the whole doorbell space for mes. Each queue in one process occupies
one doorbell slot to ring the queue submitting.

Signed-off-by: Jack Xiao <Jack.Xiao@amd.com>
Acked-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2 years agodrm/amdgpu/gmc10: skip emitting pasid mapping packet
Jack Xiao [Fri, 20 Mar 2020 06:11:04 +0000 (14:11 +0800)]
drm/amdgpu/gmc10: skip emitting pasid mapping packet

For MES FW manages IH_VMID_x_LUT updating, skip emitting pasid
mapping packet.

Signed-off-by: Jack Xiao <Jack.Xiao@amd.com>
Acked-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2 years agodrm/amdgpu/gfx10: use INVALIDATE_TLBS to invalidate TLBs v2
Jack Xiao [Fri, 20 Mar 2020 04:21:14 +0000 (12:21 +0800)]
drm/amdgpu/gfx10: use INVALIDATE_TLBS to invalidate TLBs v2

For MES queue VM flush, use INVALIDATE_TLBS to invalidate TLBs.
This packet can let CP firmware to determine the current vmid
and inv eng to invalidate.

v2: unify invalidate_tlbs functions

Cc: Le Ma <le.ma@amd.com>
Signed-off-by: Jack Xiao <Jack.Xiao@amd.com>
Acked-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2 years agodrm/amdgpu/gfx10: inherit vmid from mqd
Jack Xiao [Fri, 20 Mar 2020 04:10:00 +0000 (12:10 +0800)]
drm/amdgpu/gfx10: inherit vmid from mqd

For MES manages vmid assignment, let vmid inherit from mqd instead of
ib packet setting.

Signed-off-by: Jack Xiao <Jack.Xiao@amd.com>
Acked-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2 years agodrm/amdgpu/gfx10: associate mes queue id with fence v2
Jack Xiao [Fri, 20 Mar 2020 04:03:08 +0000 (12:03 +0800)]
drm/amdgpu/gfx10: associate mes queue id with fence v2

Associate mes queue id with fence, so that EOP trap handler can look up
which queue has issued the fence.

v2: move mes queue flag to amdgpu_mes_ctx.h

Signed-off-by: Jack Xiao <Jack.Xiao@amd.com>
Acked-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2 years agodrm/amdgpu/gfx10: use per ctx CSA for de metadata
Jack Xiao [Fri, 20 Mar 2020 03:37:31 +0000 (11:37 +0800)]
drm/amdgpu/gfx10: use per ctx CSA for de metadata

As MES requires per context preemption, use per context CSA address
for DE metadata to correctly enable context MCBP preemption.

Signed-off-by: Jack Xiao <Jack.Xiao@amd.com>
Acked-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2 years agodrm/amdgpu/gfx10: use per ctx CSA for ce metadata
Jack Xiao [Fri, 20 Mar 2020 03:10:20 +0000 (11:10 +0800)]
drm/amdgpu/gfx10: use per ctx CSA for ce metadata

As MES requires per context preemption, use per context CSA address
for CE metadata to correctly enable context MCBP preemption.

Signed-off-by: Jack Xiao <Jack.Xiao@amd.com>
Acked-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2 years agodrm/amdgpu/gfx10: implement mqd functions of gfx/compute eng v2
Jack Xiao [Wed, 1 Jul 2020 05:32:36 +0000 (13:32 +0800)]
drm/amdgpu/gfx10: implement mqd functions of gfx/compute eng v2

Refine the existing gfx/compute mqd functions, and add them
to engine mqd layer.

v2: rebase fix.

Signed-off-by: Jack Xiao <Jack.Xiao@amd.com>
Acked-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2 years agodrm/amdgpu: assign the cpu/gpu address of fence from ring
Jack Xiao [Fri, 20 Mar 2020 05:59:48 +0000 (13:59 +0800)]
drm/amdgpu: assign the cpu/gpu address of fence from ring

assign the cpu/gpu address of fence for the normal or mes ring
from ring structure.

Signed-off-by: Jack Xiao <Jack.Xiao@amd.com>
Acked-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2 years agodrm/amdgpu: initialize/finalize the ring for mes queue
Jack Xiao [Wed, 30 Mar 2022 14:04:38 +0000 (22:04 +0800)]
drm/amdgpu: initialize/finalize the ring for mes queue

Iniailize/finalize the ring for mes queue which submits the command
stream to the mes-managed hardware queue.

Signed-off-by: Jack Xiao <Jack.Xiao@amd.com>
Acked-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2 years agodrm/amdgpu: use ring structure to access rptr/wptr v2
Jack Xiao [Fri, 20 Mar 2020 02:54:45 +0000 (10:54 +0800)]
drm/amdgpu: use ring structure to access rptr/wptr v2

Use ring structure to access the cpu/gpu address of rptr/wptr.

v2: merge gfx10/sdma5/sdma5.2 patches

Signed-off-by: Jack Xiao <Jack.Xiao@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2 years agodrm/amdgpu: define ring structure to access rptr/wptr/fence
Jack Xiao [Thu, 11 Jun 2020 03:27:47 +0000 (11:27 +0800)]
drm/amdgpu: define ring structure to access rptr/wptr/fence

Define ring structure to access the cpu/gpu address of rptr/wptr/fence
instead of dynamic calculation.

Signed-off-by: Jack Xiao <Jack.Xiao@amd.com>
Acked-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2 years agodrm/amdgpu: add mes ctx data in amdgpu_ring
Jack Xiao [Mon, 16 Mar 2020 09:12:23 +0000 (17:12 +0800)]
drm/amdgpu: add mes ctx data in amdgpu_ring

Add mes context data structure in amdgpu_ring.

Signed-off-by: Jack Xiao <Jack.Xiao@amd.com>
Acked-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2 years agodrm/amdgpu: add the per-context meta data v3
Jack Xiao [Thu, 26 Mar 2020 16:38:05 +0000 (00:38 +0800)]
drm/amdgpu: add the per-context meta data v3

The per-context meta data is a per-context data structure associated
with a mes-managed hardware ring, which includes MCBP CSA, ring buffer
and etc.

v2: fix typo
v3: a. use structure instead of typedef
    b. move amdgpu_mes_ctx_get_offs_* to amdgpu_ring.h
    c. use __aligned to make alignement

Signed-off-by: Jack Xiao <Jack.Xiao@amd.com>
Acked-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2 years agodrm/amdgpu: add helper function to initialize mqd from ring v4
Jack Xiao [Wed, 1 Jul 2020 04:23:06 +0000 (12:23 +0800)]
drm/amdgpu: add helper function to initialize mqd from ring v4

Add the helper function to initialize mqd from ring configuration.

v2: use if/else pair instead of ?/: pair
v3: use simpler way to judge hqd_active
v4: fix parameters to amdgpu_gfx_is_high_priority_compute_queue

Signed-off-by: Jack Xiao <Jack.Xiao@amd.com>
Acked-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2 years agodrm/amdgpu: define MQD abstract layer for hw ip
Jack Xiao [Wed, 1 Jul 2020 03:48:52 +0000 (11:48 +0800)]
drm/amdgpu: define MQD abstract layer for hw ip

Define MQD abstract layer for hw ip, for the passing
mqd configuration not only from ring but more sources,
like user queue.

Signed-off-by: Jack Xiao <Jack.Xiao@amd.com>
Acked-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2 years agodrm/amdgpu: add imu fw structure
Likun Gao [Wed, 23 Jun 2021 09:53:35 +0000 (17:53 +0800)]
drm/amdgpu: add imu fw structure

Add IMU firmware structure.

Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2 years agodrm/amdgpu: add rlc TOC header file for soc21 (v2)
Likun Gao [Sun, 27 Jun 2021 14:33:29 +0000 (22:33 +0800)]
drm/amdgpu: add rlc TOC header file for soc21 (v2)

Add RLC autoload TOC header file for soc21 ASIC.

v2: squash in updates

Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2 years agodrm/amdgpu: add FGCG support
Evan Quan [Thu, 7 Apr 2022 13:51:41 +0000 (09:51 -0400)]
drm/amdgpu: add FGCG support

Add the CG flag for Fine Grained Clock Gating.

Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Evan Quan <evan.quan@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2 years agodrm/amdgpu: support rlc v2_3 ucode struct
Likun Gao [Mon, 30 Aug 2021 03:07:59 +0000 (11:07 +0800)]
drm/amdgpu: support rlc v2_3 ucode struct

Add support for rlc v2_3 to support RLCV and RLCP fw load.

Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Reviewed-by: Kenneth Feng <kenneth.feng@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2 years agodrm/amdgpu: add gfx firmware header v2_0
Likun Gao [Tue, 25 May 2021 03:13:27 +0000 (11:13 +0800)]
drm/amdgpu: add gfx firmware header v2_0

We need define new firmware header to support
CP RS64 fw.

Signed-off-by: Wenhui Sheng <Wenhui.Sheng@amd.com>
Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2 years agodrm/amdgpu: add irq src id for GFX11
Wenhui Sheng [Fri, 16 Oct 2020 08:11:25 +0000 (16:11 +0800)]
drm/amdgpu: add irq src id for GFX11

Signed-off-by: Wenhui Sheng <Wenhui.Sheng@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2 years agodrm/amdgpu: add gfx11 mqd structures
Hawking Zhang [Wed, 7 Jul 2021 08:33:34 +0000 (16:33 +0800)]
drm/amdgpu: add gfx11 mqd structures

memory queue descriptors for gfx11.

Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Likun Gao <Likun.Gao@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2 years agodrm/amdgpu: add gfx11 clearstate header
Hawking Zhang [Wed, 6 Jan 2021 10:47:02 +0000 (18:47 +0800)]
drm/amdgpu: add gfx11 clearstate header

Add gfx11 clearstate register arrays

Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2 years agodrm/amdgpu: add soc21 chip enum header v8
Hawking Zhang [Sun, 20 Feb 2022 10:37:12 +0000 (18:37 +0800)]
drm/amdgpu: add soc21 chip enum header v8

add soc21 enum definitions (Hawking)

Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Likun Gao <Likun.Gao@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2 years agodrm/amdgpu/discovery: Set GC family for GC 11.0 IP
Likun Gao [Mon, 4 Apr 2022 20:45:16 +0000 (16:45 -0400)]
drm/amdgpu/discovery: Set GC family for GC 11.0 IP

Set GC family for GC 11.0 IPs.

Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2 years agodrm/amdgpu: add GC v11_0_0 family id
Hawking Zhang [Tue, 22 Feb 2022 05:38:51 +0000 (13:38 +0800)]
drm/amdgpu: add GC v11_0_0 family id

Add GC v11_0_0 family id

Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Likun Gao <Likun.Gao@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2 years agodrm/amdgpu/ucode: Remove firmware load type check in amdgpu_ucode_free_bo
Alice Wong [Mon, 2 May 2022 15:40:18 +0000 (11:40 -0400)]
drm/amdgpu/ucode: Remove firmware load type check in amdgpu_ucode_free_bo

When psp_hw_init failed, it will set the load_type to AMDGPU_FW_LOAD_DIRECT.
During amdgpu_device_ip_fini, amdgpu_ucode_free_bo checks that load_type is
AMDGPU_FW_LOAD_DIRECT and skips deallocating fw_buf causing memory leak.
Remove load_type check in amdgpu_ucode_free_bo.

Signed-off-by: Alice Wong <shiwei.wong@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2 years agodrm/amd/display: Fix null pointer exception while load amdgpu
Sung Joon Kim [Fri, 29 Apr 2022 20:34:15 +0000 (16:34 -0400)]
drm/amd/display: Fix null pointer exception while load amdgpu

Recently we got a hard hang during the boot on DCN 3.0.1,
which caused the below null pointer exception:

[ +0.000426] BUG: kernel NULL pointer dereference, address: 0000000000000000
[ +0.000003] #PF: supervisor read access in kernel mode
[ +0.000003] #PF: error_code(0x0000) - not-present page
[ +0.000003] PGD 0 P4D 0
[ +0.000004] Oops: 0000 [#1] PREEMPT SMP NOPTI
[ +0.000005] CPU: 6 PID: 874 Comm: Xorg Not tainted 5.16.0.asdn-apr28+ #15
[ +0.000004] Hardware name: AMD Chachani-VN/Chachani-VN, BIOS WCH2303N 03/03/2022
[ +0.000003] RIP: 0010:resource_map_pool_resources+0x431/0xa70 [amdgpu]
[ +0.000356] Code: c1 4d 89 c8 49 c1 e0 07 4d 01 c8 49 c1 e0 04 4d 01 f0 49 83 b8 f0 01 00 00 00 0f 85 16 02 00 00 49 8b b8 e0 02 00 00 89 45 c0 <48> 8b 17 4c 8b 92 a0 01 00 00 4d 85 d2 74 24 4c 89 4d 88 48 8d 4d
[ +0.000003] RSP: 0018:ffffa92a4142f718 EFLAGS: 00010246
[ +0.000003] RAX: 0000000000000000 RBX: ffff9a0b86d93000 RCX: 0000000000000000
[ +0.000002] RDX: 0000000000000000 RSI: 000000000000554b RDI: 0000000000000000
[ +0.000002] RBP: ffffa92a4142f798 R08: ffff9a0bdb3c0000  0000000000000000
[ +0.000002] R10: 0000000000000000 R11: 000000000000f000 R12: 0000000000000000
[ +0.000001] R13: ffff9a0b88360000 R14: ffff9a0bdb3c0000 R15: ffff9a0b86273000
[ +0.000003] FS: 00007f4b5641ca40(0000) GS:ffff9a0cb7f80000(0000) knlGS:0000000000000000
[ +0.000002] CS: 0010 DS: 0000 ES: 0000 CR0: 0000000080050033
[ +0.000002] CR2: 0000000000000000 CR3: 0000000102cb2000 CR4: 00000000003506e0
[ +0.000003] Call Trace:
[ +0.000002] <TASK>
[ +0.000004] ? kvmalloc_node+0x5c/0x90
[ +0.000009] dcn20_add_stream_to_ctx+0x1c/0x90 [amdgpu]
[ +0.000330] dcn30_add_stream_to_ctx+0xe/0x10 [amdgpu]
[ +0.000313] dc_add_stream_to_ctx+0x67/0x80 [amdgpu]
[ +0.000300] dm_update_crtc_state+0x4dd/0x6e0 [amdgpu]
[ +0.000320] amdgpu_dm_atomic_check+0x63b/0x1270 [amdgpu]
[ +0.000311] ? __drm_mode_object_add+0x90/0xc0 [drm]
[ +0.000043] ? preempt_count_add+0x74/0xc0
[ +0.000005] ? _raw_spin_lock_irqsave+0x2a/0x60
[ +0.000006] ? _raw_spin_unlock_irqrestore+0x29/0x3d
[ +0.000003] ? drm_connector_list_iter_next+0x8e/0xb0 [drm]
[ +0.000038] drm_atomic_check_only+0x5dd/0xa20 [drm]
[ +0.000044] drm_atomic_commit+0x18/0x60 [drm]
[ +0.000046] drm_client_modeset_commit_atomic+0x1e5/0x220 [drm]
[ +0.000051] drm_client_modeset_commit_locked+0x57/0x160 [drm]
[ +0.000038] __drm_fb_helper_restore_fbdev_mode_unlocked+0x60/0xd0 [drm_kms_helper]
[ +0.000027] drm_fb_helper_set_par+0x40/0x50 [drm_kms_helper]
[ +0.000022] fb_set_var+0x1c8/0x3d0
[ +0.000007] ? __ext4_mark_inode_dirty+0x83/0x210
[ +0.000006] ? __ext4_journal_stop+0x3c/0xb0
[ +0.000008] fbcon_blank+0x228/0x290
[ +0.000007] do_unblank_screen+0xae/0x150
[ +0.000005] vt_ioctl+0xcf4/0x1360
[ +0.000005] ? get_max_files+0x20/0x20
[ +0.000005] ? get_max_files+0x20/0x20
[ +0.000004] ? debug_smp_processor_id+0x17/0x20
[ +0.000004] tty_ioctl+0x373/0x8a0
[ +0.000005] ? __fput+0x123/0x260
[ +0.000004] ? __fget_light+0xc5/0x100
[ +0.000005] __x64_sys_ioctl+0x91/0xc0
[ +0.000005] do_syscall_64+0x3b/0xc0
[ +0.000005] entry_SYSCALL_64_after_hwframe+0x44/0xae

This issue happens because "pipe_ctx->stream_res.tg"
needs to be initialized first before reading its members.
This commit fixes this issue by properly initializing
the pointer before accessing the target data.

Fixes: 663d2daeaee6 ("drm/amd/display: Add odm seamless boot support")
Cc: Agustin Gutierrez <agustin.gutierrez@amd.com>
Signed-off-by: Sung Joon Kim <Sungjoon.Kim@amd.com>
Reviewed-by: Agustin Gutierrez <agustin.gutierrez@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2 years agodrm/amdgpu/discovery: Enable SMU for SMU 13.0.0
Likun Gao [Mon, 4 Apr 2022 20:59:56 +0000 (16:59 -0400)]
drm/amdgpu/discovery: Enable SMU for SMU 13.0.0

Enable SMU on SMU IP version 13.0.0

Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2 years agodrm/amdgpu/soc21: enable ATHUB and MMHUB PG
Evan Quan [Thu, 7 Apr 2022 05:31:32 +0000 (01:31 -0400)]
drm/amdgpu/soc21: enable ATHUB and MMHUB PG

Enable ATHUB and MMHUB powergating.

Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2 years agodrm/amd/smu: Update SMU13 support for SMU 13.0.0
Evan Quan [Wed, 6 Apr 2022 21:13:54 +0000 (17:13 -0400)]
drm/amd/smu: Update SMU13 support for SMU 13.0.0

Modify the common smu13 code and add a new smu
13.0.0 ppt file to handle the smu 13.0.0 specific
configuration.

v2: squash in typo fix in profile name

Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Lijo Lazar <lijo.lazar@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2 years agodrm/amd/smu: add smu v13_0 header files
Likun Gao [Wed, 6 Apr 2022 21:08:50 +0000 (17:08 -0400)]
drm/amd/smu: add smu v13_0 header files

Add driver_if ppsmc and pptable header files
for smu v13_0_0

Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2 years agodrm/amd/pm: enable the support for retrieving combo pptable
Evan Quan [Wed, 6 Apr 2022 22:00:16 +0000 (18:00 -0400)]
drm/amd/pm: enable the support for retrieving combo pptable

We need to relay on this way to get the raw PPTable when
SCPM feature is enabled.

Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2 years agodrm/amd/pm: correct SMU OverridePcieParameters related settings
Evan Quan [Wed, 6 Apr 2022 21:47:20 +0000 (17:47 -0400)]
drm/amd/pm: correct SMU OverridePcieParameters related settings

Correct the hw initialization sequence.

Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Lijo Lazar <lijo.lazar@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2 years agodrm/amd/pm: enable SCPM support for SMU
Evan Quan [Wed, 6 Apr 2022 21:44:44 +0000 (17:44 -0400)]
drm/amd/pm: enable SCPM support for SMU

With SCPM enabled, the pptable used will be signed. It cannot
be used directly by driver. To get the raw pptable, we need to
rely on the combo pptable(and its revelant SMU message).

Also, the pptable transferring(to SMU) will be performed by PSP.
Some SMU messages will be not available to driver any more.

Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2 years agodrm/amdgpu: enable pptable ucode loading
Evan Quan [Wed, 6 Apr 2022 21:34:57 +0000 (17:34 -0400)]
drm/amdgpu: enable pptable ucode loading

With SCPM enabled, pptable cannot be uploaded to SMU directly.
The transferring has to be via PSP.

Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2 years agodrm/amd/pm: update the hw initialization sequence around pptable setup
Evan Quan [Thu, 17 Mar 2022 06:15:06 +0000 (14:15 +0800)]
drm/amd/pm: update the hw initialization sequence around pptable setup

Place pptable setup after smu_set_driver_table_location. As under SCPM
enabled scenario, the latter one is a prerequisite for the former one.

Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2 years agodrm/amd/pm: correct the way for retrieving bootup clocks
Evan Quan [Thu, 24 Feb 2022 08:14:14 +0000 (16:14 +0800)]
drm/amd/pm: correct the way for retrieving bootup clocks

The bootup clocks can be retrieved from the smu_info table. That
is light-weight compared with existing way.

Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Kenneth Feng <kenneth.feng@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2 years agodrm/amd/pm: move bootup values retrieving to ->sw_init
Evan Quan [Thu, 31 Mar 2022 22:10:35 +0000 (18:10 -0400)]
drm/amd/pm: move bootup values retrieving to ->sw_init

Firsrt of all, the operations involved is to interact with
VBIOS. They are fully supported at ->sw_init phase.

Secondly, the new mechanism to upload pptable to SMU is
introduced. With the new mechanism, the pptable transferring
has to be via PSP. That requires the pptable ucode(and necessary
bootupp values retrieving) must be ready before ->hw_init phase of PSP.

Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2 years agodrm/amd/pm: fix NULL pointer issue of amdgpu_smu_stb_debug_fs_init
Likun Gao [Wed, 12 Jan 2022 07:38:24 +0000 (15:38 +0800)]
drm/amd/pm: fix NULL pointer issue of amdgpu_smu_stb_debug_fs_init

Fix NULL pointer issue on amdgpu_smu_stb_debug_fs_init if SMU block not
enabled.

Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2 years agodrm/amd/pm: enable pp_dpm_vclk/dclk sysfs interface support for SMU 13.0.0
Evan Quan [Fri, 18 Mar 2022 06:35:05 +0000 (14:35 +0800)]
drm/amd/pm: enable pp_dpm_vclk/dclk sysfs interface support for SMU 13.0.0

Make the pp_dpm_vclk/dclk sysfs interfaces visible for SMU 13.0.0.

Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Lijo Lazar <lijo.lazar@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2 years agodrm/amdgpu: query core refclk from bios for smu v13
Hawking Zhang [Sun, 23 Jan 2022 11:12:30 +0000 (19:12 +0800)]
drm/amdgpu: query core refclk from bios for smu v13

The smu_info structrue for smu v13 is changed that
core_refclk in v31 strucuture is not correct for
smu v13_0_0

Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Likun Gao <Likun.Gao@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2 years agodrm/amdgpu: add updated smu_info structures
Hawking Zhang [Sun, 23 Jan 2022 11:08:25 +0000 (19:08 +0800)]
drm/amdgpu: add updated smu_info structures

To match with smu v13_0_0

Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Likun Gao <Likun.Gao@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2 years agodrm/amdgpu/discovery: add GMC 11.0 Support
Likun Gao [Mon, 4 Apr 2022 20:57:54 +0000 (16:57 -0400)]
drm/amdgpu/discovery: add GMC 11.0 Support

Enable GMC 11.0 on asics where it is present.

Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2 years agodrm/amdgpu: add gmc v11_0 ip block (v3)
Tianci.Yin [Wed, 6 Apr 2022 18:11:38 +0000 (14:11 -0400)]
drm/amdgpu: add gmc v11_0 ip block (v3)

Add support for GPU memory controller v11.

v1: Add support for gmc v11.0
    Add gmc 11 block (Tianci)
v2: drop unused amdgpu_bo_late_init (Hawking)
v3: squash in various fix

Signed-off-by: Tianci.Yin <tianci.yin@amd.com>
Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2 years agodrm/amdgpu: save the setting of VM_CONTEXT_CNTL
Jack Xiao [Wed, 12 May 2021 07:53:48 +0000 (15:53 +0800)]
drm/amdgpu: save the setting of VM_CONTEXT_CNTL

MES firmware needs the setting of VM_CONTEXT_CNTL to perform
vmid switch. Save the initial setting when hub initializing.

Signed-off-by: Jack Xiao <Jack.Xiao@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2 years agodrm/amdgpu: add mmhub v3_0 ip block
Tianci.Yin [Mon, 12 Oct 2020 10:10:13 +0000 (18:10 +0800)]
drm/amdgpu: add mmhub v3_0 ip block

Add support for mmhub v3.0

Signed-off-by: Tianci.Yin <tianci.yin@amd.com>
Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2 years agodrm/amdgpu: add mmhub v3_0_0 ip headers v6
Hawking Zhang [Thu, 18 Nov 2021 05:42:36 +0000 (13:42 +0800)]
drm/amdgpu: add mmhub v3_0_0 ip headers v6

Add mmhub v3_0_0 register offset and shift masks
header files (Hawking)

Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Likun Gao <Likun.Gao@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2 years agodrm/amdgpu: add gfxhub v3_0 ip block
Tianci.Yin [Mon, 12 Oct 2020 10:08:11 +0000 (18:08 +0800)]
drm/amdgpu: add gfxhub v3_0 ip block

Add support for gfxhub v3.0

Signed-off-by: Tianci.Yin <tianci.yin@amd.com>
Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2 years agodrm/amdgpu: add athub v3_0 ip block
Tianci.Yin [Mon, 12 Oct 2020 10:12:56 +0000 (18:12 +0800)]
drm/amdgpu: add athub v3_0 ip block

Add support for athub v3.0

Signed-off-by: Tianci.Yin <tianci.yin@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2 years agodrm/amdgpu: add athub v3_0_0 ip headers v6
Hawking Zhang [Thu, 30 Dec 2021 08:50:57 +0000 (16:50 +0800)]
drm/amdgpu: add athub v3_0_0 ip headers v6

Add athub v3_0_0 register offset and shift masks
header files (Hawking)

Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Likun Gao <Likun.Gao@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2 years agodrm/amdgpu/discovery: Enable PSP for PSP 13.0.0
Likun Gao [Mon, 4 Apr 2022 20:52:08 +0000 (16:52 -0400)]
drm/amdgpu/discovery: Enable PSP for PSP 13.0.0

Enable PSP on PSP IP version 13.0.0

Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2 years agodrm/amdgpu: add tracking for the enablement of SCPM
Likun Gao [Wed, 4 May 2022 13:56:33 +0000 (09:56 -0400)]
drm/amdgpu: add tracking for the enablement of SCPM

Add parmeter to shows whether SCPM feature is enabled or not, and
whether is valid.

Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2 years agodrm/amdgpu: rework psp firmware name
Likun Gao [Wed, 8 Dec 2021 08:19:52 +0000 (16:19 +0800)]
drm/amdgpu: rework psp firmware name

Use the new helper for deriving the fw name from
the IP version.

Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2 years agodrm/amdgpu: support psp v13_0_0 microcode init
Likun Gao [Wed, 30 Jun 2021 09:54:30 +0000 (17:54 +0800)]
drm/amdgpu: support psp v13_0_0 microcode init

Support psp v13_0_0 microcode init.

Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2 years agodrm/amdgpu: add support for spl fw load on psp v13
Likun Gao [Wed, 30 Jun 2021 09:43:21 +0000 (17:43 +0800)]
drm/amdgpu: add support for spl fw load on psp v13

Support for spl firmware load on psp v13.

Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2 years agodrm/amdgpu: extend PSP GFX FW type
Likun Gao [Wed, 1 Sep 2021 07:26:54 +0000 (15:26 +0800)]
drm/amdgpu: extend PSP GFX FW type

Extend PSP GFX FW type to support IMU, LSDMA, SDMA v6, RS64 MES related
fw load.

Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2 years agodrm/amdgpu: support print psp v2_0 hdr debug information
Hawking Zhang [Tue, 31 Aug 2021 09:23:23 +0000 (17:23 +0800)]
drm/amdgpu: support print psp v2_0 hdr debug information

print out psp firmware v2_0 hdr information for debugging
purpose

Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Le Ma <le.ma@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2 years agodrm/amdgpu/psp: deallocate memory when psp_load_fw failed
Alice Wong [Thu, 28 Apr 2022 01:03:54 +0000 (21:03 -0400)]
drm/amdgpu/psp: deallocate memory when psp_load_fw failed

psp_load_fw failure would cause memory leak for psp tmr and psp ring
because psp_hw_init is not called as psp block is not fully initialized.
Clean up psp tmr and psp ring when psp_load_fw fail by calling
psp_free_shared_bufs and psp_ring_destroy.

Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alice Wong <shiwei.wong@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2 years agodrm/amdgpu/psp: move shared buffer frees into single function
Alex Deucher [Fri, 22 Apr 2022 21:19:29 +0000 (17:19 -0400)]
drm/amdgpu/psp: move shared buffer frees into single function

So we can properly clean up if any of the TAs or TMR fails
to properly initialize or terminate.  This avoids any
memory leaks in the error case.

Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2 years agodrm/amdgpu/psp: fix memory leak in terminate functions
Alex Deucher [Fri, 22 Apr 2022 20:51:00 +0000 (16:51 -0400)]
drm/amdgpu/psp: fix memory leak in terminate functions

Make sure we free the memory even if the unload fails.

Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2 years agodrm/amdgpu/psp: drop load/unload/init_shared_buf wrappers
Alex Deucher [Fri, 22 Apr 2022 20:46:24 +0000 (16:46 -0400)]
drm/amdgpu/psp: drop load/unload/init_shared_buf wrappers

Just call the load/unload/init_shared_buf functions
directly.  Makes the code easier to follow.

Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2 years agodrm/amd/pm: Disable fan control if not supported
Elena Sakhnovitch [Fri, 11 Mar 2022 19:03:09 +0000 (14:03 -0500)]
drm/amd/pm: Disable fan control if not supported

On Sienna Cichild, not all platforms use PMFW based fan control
(ex: fanless systems). On such ASICs fan control by PMFW will be
disabled in PPTable. Disable hwmon knobs for fan control also as
it is not possible to report or control fan speed on such platforms
through driver.

v3: FeaturesToRun casted as uint64_t

Signed-off-by: Elena Sakhnovitch <elena.sakhnovitch@amd.com>
Reviewed-by: Lijo Lazar <lijo.lazar@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2 years agodrm/amdgpu: init smuio v13_0_6 callbacks
Hawking Zhang [Sat, 8 Jan 2022 09:13:37 +0000 (17:13 +0800)]
drm/amdgpu: init smuio v13_0_6 callbacks

initialize smuio callback for soc21

Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Lijo Lazar <lijo.lazar@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2 years agodrm/amdgpu/psp: move PSP memory alloc from hw_init to sw_init
Alex Deucher [Thu, 21 Apr 2022 05:21:52 +0000 (01:21 -0400)]
drm/amdgpu/psp: move PSP memory alloc from hw_init to sw_init

Memory allocations should be done in sw_init.  hw_init should
just be hardware programming needed to initialize the IP block.
This is how most other IP blocks work.  Move the GPU memory
allocations from psp hw_init to psp sw_init and move the memory
free to sw_fini.  This also fixes a potential GPU memory leak
if psp hw_init fails.

Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2 years agodrm/amdgpu: add smuio v13_0_6 support
Hawking Zhang [Sat, 8 Jan 2022 09:26:32 +0000 (17:26 +0800)]
drm/amdgpu: add smuio v13_0_6 support

add smuio v13_0_6 callbacks to support read
rom image

Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Lijo Lazar <lijo.lazar@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2 years agodrm/amdgpu: add smuio v13_0_6 ip headers v4
Hawking Zhang [Thu, 30 Dec 2021 11:25:29 +0000 (19:25 +0800)]
drm/amdgpu: add smuio v13_0_6 ip headers v4

Add smuio v13_0_6 register offset and shift masks
header files (Hawking)

Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Likun Gao <Likun.Gao@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2 years agodrm/amdgpu: Remove trailing space
Elena Sakhnovitch [Thu, 28 Apr 2022 23:26:29 +0000 (19:26 -0400)]
drm/amdgpu: Remove trailing space

Clean up trailing space in file sienna_cichlid_ppt.c.

Signed-off-by: Elena Sakhnovitch <elena.sakhnovitch@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2 years agodrm/amdgpu/discovery: add HDP v6
Likun Gao [Mon, 4 Apr 2022 20:48:30 +0000 (16:48 -0400)]
drm/amdgpu/discovery: add HDP v6

Enable HDP v6 on asics where it is present.

Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2 years agodrm/amdgpu: add hdp version 6 functions
Likun Gao [Mon, 4 Apr 2022 21:29:28 +0000 (17:29 -0400)]
drm/amdgpu: add hdp version 6 functions

Unify hdp related function into hdp structure for hdp version 6.
V2: Remove hdp invalidate function as hdp v6 doesn't have read cache.

Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2 years agodrm/amdgpu: Free user pages if kvmalloc_array fails
Philip Yang [Fri, 29 Apr 2022 00:17:38 +0000 (20:17 -0400)]
drm/amdgpu: Free user pages if kvmalloc_array fails

To cleanup the BOs of bo_list which have got user pages.

Signed-off-by: Philip Yang <Philip.Yang@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2 years agodrm/amdgpu: add hdp v6_0_0 ip headers v4
Hawking Zhang [Thu, 30 Dec 2021 09:00:10 +0000 (17:00 +0800)]
drm/amdgpu: add hdp v6_0_0 ip headers v4

Add hdp v6_0_0 register offset and shift masks
header files (Hawking)

Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Likun Gao <Likun.Gao@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2 years agogpu/drm/radeon: Fix spelling typo in comments
pengfuyuan [Fri, 29 Apr 2022 01:51:14 +0000 (09:51 +0800)]
gpu/drm/radeon: Fix spelling typo in comments

Fix spelling typo in comments.

Signed-off-by: pengfuyuan <pengfuyuan@kylinos.cn>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2 years agodrm/amdgpu: simplify the return expression of navi10_ih_hw_init()
Minghao Chi [Fri, 29 Apr 2022 05:50:37 +0000 (05:50 +0000)]
drm/amdgpu: simplify the return expression of navi10_ih_hw_init()

Simplify the return expression.

Reported-by: Zeal Robot <zealci@zte.com.cn>
Signed-off-by: Minghao Chi <chi.minghao@zte.com.cn>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2 years agodrm/amdgpu: simplify the return expression of iceland_ih_hw_init
Minghao Chi [Fri, 29 Apr 2022 05:48:41 +0000 (05:48 +0000)]
drm/amdgpu: simplify the return expression of iceland_ih_hw_init

Simplify the return expression.

Reported-by: Zeal Robot <zealci@zte.com.cn>
Signed-off-by: Minghao Chi <chi.minghao@zte.com.cn>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2 years agodrm/amdgpu/discovery: add IH v6
Likun Gao [Mon, 4 Apr 2022 20:50:39 +0000 (16:50 -0400)]
drm/amdgpu/discovery: add IH v6

Enable IH v6 on asics where it is present.

Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2 years agodrm/amdgpu: add ih v6_0 ip block v2
Stanley.Yang [Tue, 22 Feb 2022 06:53:16 +0000 (14:53 +0800)]
drm/amdgpu: add ih v6_0 ip block v2

This adds ih v6_0 ip block support.  IH is the
interrupt handler.

Signed-off-by: Stanley.Yang <Stanley.Yang@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2 years agodrm/amd/smu: Increace dpm level count only for smu v13.0.2
Likun Gao [Fri, 29 Apr 2022 04:03:53 +0000 (12:03 +0800)]
drm/amd/smu: Increace dpm level count only for smu v13.0.2

Only V13.0.2 on SMU v13 will get 0 based max level from fw and
increment by one, other ASIC will not need for this.
V2: replace the asic_type check with ip versioning check.

Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2 years agodrm/amdgpu: add soc21 ih clientid definition
Stanley Yang [Tue, 22 Feb 2022 08:35:39 +0000 (16:35 +0800)]
drm/amdgpu: add soc21 ih clientid definition

Define soc21 ih clientid

Signed-off-by: Stanley Yang <Stanley.Yang@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2 years agodrm/amdgpu: add osssys v6_0_0 ip headers v4
Hawking Zhang [Thu, 30 Dec 2021 11:21:43 +0000 (19:21 +0800)]
drm/amdgpu: add osssys v6_0_0 ip headers v4

Add osssys v6_0_0 register offset and shift masks
header files (Hawking)

Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Likun Gao <Likun.Gao@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2 years agodrm/amdgpu/discovery: add NBIO 4.3 Support
Likun Gao [Mon, 4 Apr 2022 20:55:18 +0000 (16:55 -0400)]
drm/amdgpu/discovery: add NBIO 4.3 Support

Enable NBIO 4.3 on asics where it is present.

Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2 years agodrm/amdgpu: add nbio v4_3_0 ip block v2
Stanley.Yang [Mon, 4 Apr 2022 21:28:13 +0000 (17:28 -0400)]
drm/amdgpu: add nbio v4_3_0 ip block v2

This adds nbio v4_3_0 ip block support

Changed from v1:
use WREG32_SOC15/RREG32_SOC15 instead of
WREG32_PCIE/RREG32_PCIE
remove the programming of PCIE_CONFIG_CNTL

Signed-off-by: Stanley.Yang <Stanley.Yang@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2 years agodrm/amdgpu: add nbio v4_3_0 ip headers v6
Hawking Zhang [Thu, 30 Dec 2021 11:18:08 +0000 (19:18 +0800)]
drm/amdgpu: add nbio v4_3_0 ip headers v6

Add nbio v4_3_0 register offset and shift masks
header files (Hawking)

Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Likun Gao <Likun.Gao@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2 years agodrm/amdgpu/discovery: add soc21 common Support
Likun Gao [Mon, 4 Apr 2022 21:04:55 +0000 (17:04 -0400)]
drm/amdgpu/discovery: add soc21 common Support

Enable soc21 common support on asics where it is present.

Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2 years agodrm/amd/display: Avoid reading audio pattern past AUDIO_CHANNELS_COUNT
Harry Wentland [Tue, 19 Apr 2022 17:03:12 +0000 (13:03 -0400)]
drm/amd/display: Avoid reading audio pattern past AUDIO_CHANNELS_COUNT

A faulty receiver might report an erroneous channel count. We
should guard against reading beyond AUDIO_CHANNELS_COUNT as
that would overflow the dpcd_pattern_period array.

Signed-off-by: Harry Wentland <harry.wentland@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2 years agodrm/amdgpu: Free user pages if amdgpu_cs_parser_bos failed
Philip Yang [Wed, 27 Apr 2022 22:50:49 +0000 (18:50 -0400)]
drm/amdgpu: Free user pages if amdgpu_cs_parser_bos failed

Otherwise userspace resubmit the BOs again will trigger kernel WARNING
and fail the command submission.

Signed-off-by: Philip Yang <Philip.Yang@amd.com>
Tested-by: Robert Święcki <robert@swiecki.net>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2 years agodrm/amdgpu: Fix build warning for TA debugfs interface
Candice Li [Wed, 27 Apr 2022 10:02:45 +0000 (18:02 +0800)]
drm/amdgpu: Fix build warning for TA debugfs interface

Remove the redundant codes to fix build warning
when CONFIG_DEBUG_FS is disabled.

Reported-by: Randy Dunlap <rdunlap@infradead.org>
Signed-off-by: Candice Li <candice.li@amd.com>
Reviewed-by: Yang Wang <kevinyang.wang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2 years agodrm/amdgpu: add soc21 common ip block v2
Stanley.Yang [Fri, 1 Apr 2022 18:41:06 +0000 (14:41 -0400)]
drm/amdgpu: add soc21 common ip block v2

This adds soc21 common ip block support

Changed from v1:
Switch WREG32/RREG32_PCIE to use indirect reg access
helper for sco15 and onwards

Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Stanley.Yang <Stanley.Yang@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2 years agodrm/amdgpu: add new write field for soc21
Stanley.Yang [Wed, 4 Aug 2021 07:43:17 +0000 (15:43 +0800)]
drm/amdgpu: add new write field for soc21

add new write field macro to handle soc21
registers with reg prefix

Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Stanley.Yang <Stanley.Yang@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2 years agodrm/amdgpu: add nbio callback to query rom offset
Hawking Zhang [Sat, 8 Jan 2022 09:18:37 +0000 (17:18 +0800)]
drm/amdgpu: add nbio callback to query rom offset

Add nbio callback func used to query rom offset.
Used to query the rom offset for fetching the vbios.

Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Lijo Lazar <lijo.lazar@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2 years agodrm/amdgpu: add gc v11_0_0 ip headers v11
Hawking Zhang [Thu, 30 Dec 2021 08:56:09 +0000 (16:56 +0800)]
drm/amdgpu: add gc v11_0_0 ip headers v11

Add gc v11_0_0 register offset and shift masks
header files (Hawking)

Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Reviewed-by: Likun Gao <Likun.Gao@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2 years agodrm/amdgpu: add mp v13_0_0 ip headers v7
Hawking Zhang [Thu, 30 Dec 2021 11:12:28 +0000 (19:12 +0800)]
drm/amdgpu: add mp v13_0_0 ip headers v7

Add mp v13_0_0 register offset and shift masks
header files (Hawking)

Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Reviewed-by: Likun Gao <Likun.Gao@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2 years agodrm/amdgpu: update query ref clk from bios
Hawking Zhang [Sun, 23 Jan 2022 10:47:47 +0000 (18:47 +0800)]
drm/amdgpu: update query ref clk from bios

Handle atom_gfx_info_v3_0 structure.

Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Likun Gao <Likun.Gao@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2 years agodrm/amdgpu: update gc info from bios table
Hawking Zhang [Thu, 7 Apr 2022 05:49:55 +0000 (01:49 -0400)]
drm/amdgpu: update gc info from bios table

Handle newer gc info tables.

Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Likun Gao <Likun.Gao@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2 years agodrm/amdgpu: add atom_gfx_info_v3_0 structure
Hawking Zhang [Sun, 23 Jan 2022 09:40:30 +0000 (17:40 +0800)]
drm/amdgpu: add atom_gfx_info_v3_0 structure

atomfirmware table used for newer gfx IPs.

Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Likun Gao <Likun.Gao@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>