From: Venkata Sandeep Dhanalakota Date: Wed, 7 Oct 2020 00:22:06 +0000 (-0700) Subject: drm/i915/dg1: Increase mmio size to 4MB X-Git-Tag: microblaze-v5.12~209^2~14^2~114 X-Git-Url: http://git.monstr.eu/?a=commitdiff_plain;h=eafeb204b4730bac1f1701183cd05c7fe2e81e0f;p=linux-2.6-microblaze.git drm/i915/dg1: Increase mmio size to 4MB On DGFX the register range has been extended to go up to 8MB. However we only actually use up to address 280000h, so let's increase it to 4MB. v2 (Lucas): add bspec reference and reword commit message to explain the 4 vs 8 MB used (requested by Matt Roper) Bspec: 53616 Cc: Daniele Ceraolo Spurio Cc: Michael J. Ruhl Signed-off-by: Venkata Sandeep Dhanalakota Signed-off-by: Lucas De Marchi Reviewed-by: Matt Roper Link: https://patchwork.freedesktop.org/patch/msgid/20201007002210.3678024-4-lucas.demarchi@intel.com --- diff --git a/drivers/gpu/drm/i915/intel_uncore.c b/drivers/gpu/drm/i915/intel_uncore.c index 263ffcb832b7..54e201fdeba4 100644 --- a/drivers/gpu/drm/i915/intel_uncore.c +++ b/drivers/gpu/drm/i915/intel_uncore.c @@ -1701,11 +1701,15 @@ static int uncore_mmio_setup(struct intel_uncore *uncore) * clobbering the GTT which we want ioremap_wc instead. Fortunately, * the register BAR remains the same size for all the earlier * generations up to Ironlake. + * For dgfx chips register range is expanded to 4MB. */ if (INTEL_GEN(i915) < 5) mmio_size = 512 * 1024; + else if (IS_DGFX(i915)) + mmio_size = 4 * 1024 * 1024; else mmio_size = 2 * 1024 * 1024; + uncore->regs = pci_iomap(pdev, mmio_bar, mmio_size); if (uncore->regs == NULL) { drm_err(&i915->drm, "failed to map registers\n");