From: Chris Wilson Date: Tue, 27 Aug 2019 12:06:15 +0000 (+0100) Subject: drm/i915/execlists: Flush the post-sync breadcrumb write harder X-Git-Tag: microblaze-v5.6-rc1~35^2~43^2~283 X-Git-Url: http://git.monstr.eu/?a=commitdiff_plain;h=e8f6b4952ec54a9d7e43f908d39dc168b0310599;p=linux-2.6-microblaze.git drm/i915/execlists: Flush the post-sync breadcrumb write harder Quite rarely we see that the CS completion event fires before the breadcrumb is coherent, which presumably is a result of the CS_STALL not waiting for the post-sync operation. Try throwing in a DC_FLUSH into the following pipecontrol to see if that makes any difference. Signed-off-by: Chris Wilson Cc: Mika Kuoppala Acked-by: Mika Kuoppala Link: https://patchwork.freedesktop.org/patch/msgid/20190827120615.31390-1-chris@chris-wilson.co.uk --- diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c b/drivers/gpu/drm/i915/gt/intel_lrc.c index a141e9e37bf7..171d5205962c 100644 --- a/drivers/gpu/drm/i915/gt/intel_lrc.c +++ b/drivers/gpu/drm/i915/gt/intel_lrc.c @@ -2923,8 +2923,10 @@ static u32 *gen8_emit_fini_breadcrumb_rcs(struct i915_request *request, u32 *cs) PIPE_CONTROL_DC_FLUSH_ENABLE); /* XXX flush+write+CS_STALL all in one upsets gem_concurrent_blt:kbl */ + /* XXX DC_FLUSH for post-sync write? (cf early context-switch bug) */ cs = gen8_emit_pipe_control(cs, PIPE_CONTROL_FLUSH_ENABLE | + PIPE_CONTROL_DC_FLUSH_ENABLE | PIPE_CONTROL_CS_STALL, 0);