From: Dmitry Baryshkov Date: Thu, 17 Oct 2024 18:04:47 +0000 (+0300) Subject: dt-bindings: PCI: qcom,pcie-sm8550: Add SAR2130P compatible X-Git-Tag: microblaze-v6.16~472^2~15^2~1 X-Git-Url: http://git.monstr.eu/?a=commitdiff_plain;h=d38cc57c14ff9590e03da77987217eca19ea350d;p=linux-2.6-microblaze.git dt-bindings: PCI: qcom,pcie-sm8550: Add SAR2130P compatible On the Qualcomm SAR2130P platform the PCIe host is compatible with the DWC controller present on the SM8550 platorm, just using one additional clock. Link: https://lore.kernel.org/r/20241017-sar2130p-pci-v1-1-5b95e63d9624@linaro.org Signed-off-by: Dmitry Baryshkov Signed-off-by: Krzysztof Wilczyński Reviewed-by: Krzysztof Kozlowski --- diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie-sm8550.yaml b/Documentation/devicetree/bindings/pci/qcom,pcie-sm8550.yaml index 24cb38673581..2b5498a35dcc 100644 --- a/Documentation/devicetree/bindings/pci/qcom,pcie-sm8550.yaml +++ b/Documentation/devicetree/bindings/pci/qcom,pcie-sm8550.yaml @@ -20,6 +20,7 @@ properties: - const: qcom,pcie-sm8550 - items: - enum: + - qcom,sar2130p-pcie - qcom,pcie-sm8650 - const: qcom,pcie-sm8550 @@ -39,7 +40,7 @@ properties: clocks: minItems: 7 - maxItems: 8 + maxItems: 9 clock-names: minItems: 7 @@ -52,6 +53,7 @@ properties: - const: ddrss_sf_tbu # PCIe SF TBU clock - const: noc_aggr # Aggre NoC PCIe AXI clock - const: cnoc_sf_axi # Config NoC PCIe1 AXI clock + - const: qmip_pcie_ahb # QMIP PCIe AHB clock interrupts: minItems: 8