From: Rodrigo Vivi <rodrigo.vivi@intel.com>
Date: Thu, 17 Oct 2024 16:52:05 +0000 (-0400)
Subject: Merge drm/drm-next into drm-intel-next
X-Git-Tag: microblaze-v6.16~14^2~17^2~279
X-Git-Url: http://git.monstr.eu/?a=commitdiff_plain;h=c141cf76918e;p=linux-2.6-microblaze.git

Merge drm/drm-next into drm-intel-next

Needed to bring some KVM changes to be able to include a fix in our Kconfig.

Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
---

c141cf76918e25ec7bd433b47590e8c3f3d02542
diff --cc drivers/gpu/drm/xe/compat-i915-headers/intel_uncore.h
index 97afa13ad4ce,ee3469d4ae73..0382beb4035b
--- a/drivers/gpu/drm/xe/compat-i915-headers/intel_uncore.h
+++ b/drivers/gpu/drm/xe/compat-i915-headers/intel_uncore.h
@@@ -152,9 -152,33 +152,9 @@@ static inline void intel_uncore_write_n
  {
  	struct xe_reg reg = XE_REG(i915_mmio_reg_offset(i915_reg));
  
- 	xe_mmio_write32(__compat_uncore_to_gt(uncore), reg, val);
+ 	xe_mmio_write32(__compat_uncore_to_mmio(uncore), reg, val);
  }
  
 -static inline void __iomem *intel_uncore_regs(struct intel_uncore *uncore)
 -{
 -	struct xe_device *xe = container_of(uncore, struct xe_device, uncore);
 -
 -	return xe_device_get_root_tile(xe)->mmio.regs;
 -}
 -
 -/*
 - * The raw_reg_{read,write} macros are intended as a micro-optimization for
 - * interrupt handlers so that the pointer indirection on uncore->regs can
 - * be computed once (and presumably cached in a register) instead of generating
 - * extra load instructions for each MMIO access.
 - *
 - * Given that these macros are only intended for non-GSI interrupt registers
 - * (and the goal is to avoid extra instructions generated by the compiler),
 - * these macros do not account for uncore->gsi_offset.  Any caller that needs
 - * to use these macros on a GSI register is responsible for adding the
 - * appropriate GSI offset to the 'base' parameter.
 - */
 -#define raw_reg_read(base, reg) \
 -	readl(base + i915_mmio_reg_offset(reg))
 -#define raw_reg_write(base, reg, value) \
 -	writel(value, base + i915_mmio_reg_offset(reg))
 -
  #define intel_uncore_forcewake_get(x, y) do { } while (0)
  #define intel_uncore_forcewake_put(x, y) do { } while (0)
  
diff --cc drivers/gpu/drm/xe/display/xe_display.c
index b1730b581656,26b2cae11d46..957ae763531d
--- a/drivers/gpu/drm/xe/display/xe_display.c
+++ b/drivers/gpu/drm/xe/display/xe_display.c
@@@ -356,9 -340,55 +344,55 @@@ static void __xe_display_pm_suspend(str
  
  	intel_opregion_suspend(display, s2idle ? PCI_D1 : PCI_D3cold);
  
 -	intel_dmc_suspend(xe);
 +	intel_dmc_suspend(display);
  }
  
+ void xe_display_pm_suspend(struct xe_device *xe)
+ {
+ 	__xe_display_pm_suspend(xe, false);
+ }
+ 
+ void xe_display_pm_shutdown(struct xe_device *xe)
+ {
+ 	struct intel_display *display = &xe->display;
+ 
+ 	if (!xe->info.probe_display)
+ 		return;
+ 
+ 	intel_power_domains_disable(xe);
+ 	intel_fbdev_set_suspend(&xe->drm, FBINFO_STATE_SUSPENDED, true);
+ 	if (has_display(xe)) {
+ 		drm_kms_helper_poll_disable(&xe->drm);
+ 		intel_display_driver_disable_user_access(xe);
+ 		intel_display_driver_suspend(xe);
+ 	}
+ 
+ 	xe_display_flush_cleanup_work(xe);
+ 	intel_dp_mst_suspend(xe);
+ 	intel_hpd_cancel_work(xe);
+ 
+ 	if (has_display(xe))
+ 		intel_display_driver_suspend_access(xe);
+ 
+ 	intel_encoder_suspend_all(display);
+ 	intel_encoder_shutdown_all(display);
+ 
+ 	intel_opregion_suspend(display, PCI_D3cold);
+ 
+ 	intel_dmc_suspend(xe);
+ }
+ 
+ void xe_display_pm_runtime_suspend(struct xe_device *xe)
+ {
+ 	if (!xe->info.probe_display)
+ 		return;
+ 
+ 	if (xe->d3cold.allowed)
+ 		__xe_display_pm_suspend(xe, true);
+ 
+ 	intel_hpd_poll_enable(xe);
+ }
+ 
  void xe_display_pm_suspend_late(struct xe_device *xe)
  {
  	bool s2idle = suspend_to_idle();